HY5V52LF-S datasheet(9/13 Pages) HYNIX

Part #	HY5V52LF-S

Description	4Banks x 2M x 32bits Synchronous DRAM

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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9 / 13 page

Rev. 0.1 / June. 2004

9

Preliminary

HY5V52(L)F(P) Series

4Banks x 2M x 32bits Synchronous DRAM

DC CHARACTERISTICS II (TA= 0 to 70oC)

Note :

1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. HY5V52F(P) Series : Normal,

HY5V52LF(P) Series : Low Power

Parameter

Symbol

Test Condition

Speed

Uni

t

Not

e

H

P

S

Operating Current

IDD1

Burst length=1, One bank active

tRC

≥ tRC(min), IOL=0mA

120

110

mA

1

Precharge Standby Current

in Power Down Mode

IDD2P

CKE

≤ VIL(max), tCK = 15ns

2

mA

IDD2PS

CKE

≤ VIL(max), tCK = ∞

1mA

Precharge Standby Current

in Non Power Down Mode

IDD2N

CKE

≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during

2clks.

All other pins

≥ VDD-0.2V or ≤ 0.2V

15

mA

IDD2NS

CKE

≥ VIH(min), tCK = ∞

Input signals are stable.

15

Active Standby Current

in Power Down Mode

IDD3P

CKE

≤ VIL(max), tCK = 15ns

5

mA

IDD3PS

CKE

≤ VIL(max), tCK = ∞

5

Active Standby Current

in Non Power Down Mode

IDD3N

CKE

≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during

2clks.

All other pins

≥ VDD-0.2V or ≤ 0.2V

30

mA

IDD3NS

CKE

≥ VIH(min), tCK = ∞

Input signals are stable.

20

Burst Mode Operating Cur-

rent

IDD4

tCK

≥ tCK(min), IOL=0mA

All banks active

CL=3

150

130

mA

1

CL=2

160

140

Auto Refresh Current

IDD5

tRC

≥ tRC(min), All banks active

220

mA

2

Self Refresh Current

IDD6

CKE

≤ 0.2V

Normal

3

mA

3

Low Power

1.5

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