IDT709079L12PF datasheet(3/17 Pages) IDT

Part #	IDT709079L12PF

Description	HIGH-SPEED 32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

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6.42

IDT709079S/L

Preliminary

High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

3

Pin Names

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. CE0 and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.

4. ADS is independent of all other signals including CE0 and CE1.

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.

Truth Table II—Address Counter Control(1,2)

Truth Table I—Read/Write and En-

able Control(1,2,3)

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

Left Port

Right Port

Names

CE0L

, CE1L

CE0R

, CE1R

Chip Enables

R/WL

R/WR

Read/Write Enable

OEL

OER

Output Enable

A0L - A14L

A0R - A14R

Address

I/O0L - I/O7L

I/O0R - I/O7R

Data Input/Output

CLKL

CLKR

Clock

ADSL

ADSR

Address Strobe

CNTENL

CNTENR

Counter Enable

CNTRSTL

CNTRSTR

Counter Reset

FT

/PIPEL

FT

/PIPER

Flow-Through/Pipeline

VCC

Power

GND

Ground

3495 tbl 01

OE

CLK

CE0

CE1

R/

W

I/O0-7

Mode

X

↑

H

X

High-Z

Deselected

X

↑

X

L

X

High-Z

Deselected

X

↑

LH

L

DIN

Write

L

↑

LH

H

DOUT

Read

H

X

L

H

X

High-Z

Outputs Disabled

3495 tbl 02

Address

Addr

Used

CLK

ADS

CNTEN

CNTRST

I/O(3)

MODE

XX

0

↑

XX

L(4)

DI/O(0)

Counter Reset to Address 0

An

X

An

↑

L(4)

XH

DI/O (n)

External Address Used

An

Ap

↑

HH

H

DI/O(p)

External Address Blocked—Counter disabled (Ap reused)

XAp

Ap + 1

↑

H

L(5)

HDI/O(p+1) Counter Enabled—Internal Address generation

3495 tbl 03

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