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HY5V52F-P Datasheet(PDF) 10 Page - Hynix Semiconductor

Part # HY5V52F-P
Description  4Banks x 2M x 32bits Synchronous DRAM
Download  13 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY5V52F-P Datasheet(HTML) 10 Page - Hynix Semiconductor

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Rev. 0.1 / June. 2004
10
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Parameter
Symbol
H
P
S
Unit Note
Min Max Min Max Min Max
System ClockCycle Time
CAS Latency=3
tCK3
7.5
1000
10
1000
10
1000
ns
CAS Latency=2
tCK2
10
10
12
ns
Clock High Pulse Width
tCHW
2.5
-
3.0
-
3.0
-
ns
1
Clock Low Pulse Width
tCLW
2.5
-
3.0
-
3.0
-
ns
1
Access Time From Clock
CAS Latency=3
tAC3
-
5.4
-6-6
ns
2
CAS Latency=2
tAC2
-6-6-6
ns
Data-out Hold Time
tOH
2.0
-
2.0
-
2.0
-
ns
Data-Input Setup Time
tDS
2.0
-
2.0
-
2.0
-
ns
1
Data-Input Hold Time
tDH
1.0
-
1.0
-
1.0
-
ns
1
Address Setup Time
tAS
2.0
-
2.0
-
2.0
-
ns
1
Address Hold Time
tAH
1.0
-
1.0
-
1.0
-
ns
1
CKE Setup Time
tCKS
2.0
-
2.0
-
2.0
-
ns
1
CKE Hold Time
tCKH
1.0
-
1.0
-
1.0
-
ns
1
Command Setup Time
tCS
2.0
-
2.0
-
2.0
-
ns
1
Command Hold Time
tCH
1.0
-
1.0
-
1.0
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1.0
-
1.0
-
1.0
-
ns
CLK to Data Output in High-
Z Time
CAS Latency=3
tOHZ3
2.0
5.4
2.0
6.0
2.0
6.0
ns
CAS Latency=2
tOHZ2
2.0
6.0
2.0
6.0
2.0
6.0
ns


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