SMS2904S datasheet(7/14 Pages) SUMMIT

Part #	SMS2904S

Description	Voltage Supervisory Circuit With Watchdog Timer

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Manufacturer	SUMMIT [Summit Microelectronics, Inc.]

Direct Link	http://www.summitmicro.com

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7 / 14 page

SMS2902/SMS2904/SMS2916

7

2028 5.1 8/2/00

FIGURE 5. ACKNOWLEDGE RESPONSE FROM RECEIVER

CHARACTERISTICS OF THE I2C BUS

General Description

The I2C bus was designed for two-way, two-line serial

communication between different integrated circuits. The

two lines are: a serial data line (SDA), and a serial clock

line (SCL). The SDA line must be connected to a positive

supply by a pull-up resistor, located somewhere on the

bus (See Figure 1). Data transfer between devices may

be initiated with a START condition only when SCL and

SDA are HIGH (bus is not busy).

Input Data Protocol

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during clock

HIGH time, because changes on the data line while SCL

is HIGH will be interpreted as start or stop condition.

START and STOP Conditions

When both the data and clock lines are HIGH, the bus is

said to be not busy. A HIGH-to-LOW transition on the data

line, while the clock is HIGH, is defined as the “START”

condition. A LOW-to-HIGH transition on the data line,

while the clock is HIGH, is defined as the “STOP” condi-

tion .

DEVICE OPERATION

The SMS29xx is a 2K/4K/16K serial E2PROM. The de-

vice supports the I2C bidirectional data transmission

protocol. The protocol defines any device that sends data

onto the bus as a “transmitter” and any device which

receives data as a “receiver.” The device controlling data

transmission is called the “master” and the controlled

device is called the “slave.” In all cases, the SMS29xx will

be a “slave” device, since it never initiates any data

transfers.

FIGURE 6. SLAVE ADDRESS BYTE

Acknowledge (ACK)

Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either

the master or the slave, will release the bus after transmit-

ting eight bits. During the ninth clock cycle, the receiver

will pull the SDA line LOW to ACKnowledge that it re-

ceived the eight bits of data (See Figure 5).

The SMS29xx will respond with an ACKnowledge after

recognition of a START condition and its slave address

byte. If both the device and a write operation are selected,

the SMS29xx will respond with an ACKnowledge after the

receipt of each subsequent 8-bit word.

In the READ mode, the SMS29xx transmits eight bits of

data, then releases the SDA line, and monitors the line for

an ACKnowledge signal. If an ACKnowledge is detected,

and no STOP condition is generated by the master, the

SMS29xx will continue to transmit data. If an

ACKnowledge is not detected, the SMS29xx will terminate

further data transmissions and awaits a STOP condition

before returning to the standby power mode.

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most significant

four bits of the slave address are the device type identifier

(‘1010’) (see figure 6).

SCL from

Master

Data Output

from

Transmitter

Data Output

from

Receiver

Start

Condition

ACKnowledge

tAA

1

8

9

2028 ILL7.0

1

0

1

0

R/W

DEVICE

IDENTIFIER

2028 ILL8.1

A

10

*

A

8

**

A

9

*

* = 2916 only

** = 2904 only

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SMS2904S Datasheet(PDF) 7 Page - Summit Microelectronics, Inc.

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