K9K2G08R0A datasheet(8/38 Pages) SAMSUNG

Part #	K9K2G08R0A

Description	FLASH MEMORY

Download	38 Pages

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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8 / 38 page

FLASH MEMORY

8

K9K2G08R0A

K9K2G08U0A

2K Bytes

64 Bytes

Figure 1. Functional Block Diagram

Figure 2 Array Organization

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

1st Cycle

A0

A1

A2

A3

A4

A5

A6

A7

2nd Cycle

A8

A9

A10

A11

*L

3rd Cycle

A12

A13

A14

A15

A16

A17

A18

A19

4th Cycle

A20

A21

A22

A23

A24

A25

A26

A27

5th Cycle

A28

*L

VCC

X-Buffers

Command

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Register

Control Logic

& High Voltage

Generator

Global Buffers

Output

Driver

VSS

A12 - A28

A0 - A11

Command

CE

RE

WE

CLE

WP

I/0 0

I/0 7

VCC

VSS

128K Pages

(=2,048 Blocks)

2K Bytes

8 bit

64 Bytes

1 Block = 64 Pages

(128K + 4k) Byte

I/O 0 ~ I/O 7

1 Page = (2K + 64)Bytes

1 Block = (2K + 64)B x 64 Pages

= (128K + 4K) Bytes

1 Device = (2K+64)B x 64Pages x 2048 Blocks

= 2112 Mbits

Row Address

Page Register

2048M + 64M Bit

NAND Flash

ARRAY

(2048 + 64)Byte x 131072

Y-Gating

Row Address

Column Address

Data Register & S/A

Row Address

ALE

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