SP8481 datasheet(6/12 Pages) SIPEX

Part #	SP8481

Description	Monolithic, 12-Bit Data Acquisition System

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Manufacturer	SIPEX [Sipex Corporation]

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306

SP8481

GAIN ADJUST

125K

Ω

+15V

10K

Ω

±0.3% Trim Range

5

19K

Ω

Center pot

for zero

correction

SP8481

OFFSET ADJUST

100K

Ω

+15V

5K

Ω

–1.5mV to +3mV

4

Figure 1. Offset Adjust

Figure 2. Gain Adjust

outputs when high and starts the conversion

when low. CS and CE may also be used with

R/C to initiate a conversion. The last of the three

inputs to reach the correct state starts the conver-

sion, therefore one, two or all three may be

dynamically controlled. The nominal delay from

all three is the same and they may change state

simultaneously. In order to ensure that a particu-

lar input controls the conversion the other two

should be set up at least 50ns earlier.

The

STATUS line indicates when a conversion is in

process and when it is complete. The A0 input is

used to configure the output data.

The conversion cycle is started when R/C is

brought low and must be held low for a minimum

of 50ns. The R/C signal will also put the output

latches in a tri-state mode when low. Approxi-

mately 200ns after R/C is low, STATUS will

change from low to high. This output signal will

stay high while the SP8481 is performing a

conversion. Valid data will be latched to the

output bus, through internal control, 500ns prior

to the STATUS line transitioning from a high to

low.

Reading the Data

The output data buffers will remain in a high

impedance state until the following four condi-

tions are met: R/C is HIGH, STATUS is LOW,

CE is HIGH and CS is LOW. The data lines

become active in response to the four conditions

and will latch data according to the conditions of

A0 line. Please refer to Figure 5 for the appropri-

ate timing. All conditions must be met at least

50ns prior to reading the data to allow sufficient

time for the output latches to come out of the high

impedance state. A0 is used to access the data.

The first 8 MSBs will be on pins 26 through 19,

with pin 26 being the MSB. The remaining 4

LSBs will be on pins 23 through 26 with pin 23

being the LSB. When A0 is switched from one

state to the next, there is a 50ns output latch

propagation delay between the MSBs and LSBs

being present on the output pins.

CALIBRATION

The calibration procedure for the SP8481 con-

sists of adjusting the most negative input voltage

(0V) to the ideal output code for offset adjust-

ment, and then adjusting the most positive input

voltage (5.0V) to its ideal output code for gain

adjustment.

Offset Adjustment

The offset adjustment must be completed first.

Please refer to Figure 1. Apply an input voltage

of 0.5LSB or 610

µV to any multiplexer input.

Adjust the offset potentiometer so that the output

code fluctuates evenly between 000…000 and

000…001. It is only necessary to observe the

lower eight LSB’s during this procedure.

Gain Adjustment

With the offset adjusted, the gain error can now

be trimmed to zero. The ideal input voltage

corresponding to 1.5 LSB’s below the nominal

full scale input value, or +4.988V, is applied to

any multiplexer input. The gain potentiometer is

adjusted so that the output code alternates evenly

between 111…111 and 111…110. Again, only

the lower eight LSB’s need be observed during

this procedure. With the above adjustment made,

the converter is now calibrated.

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