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IR2161S Datasheet(PDF) 10 Page - International Rectifier |
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IR2161S Datasheet(HTML) 10 Page - International Rectifier |
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10 / 19 page  IR2161(S) 10 www.irf.com ADVANCE DATA across the CSD capacitor will vary from 0V if there is no load to approximately 5V at maximum load. This is provided that the correct value of current sense resistor has been selected for the maximum rated load and line voltage supply of the convertor. This should be 0.33 Ohm (0.5W) for a 100W system running from a 220-240V AC line. (It should be noted that the RCS resistor value is also critical for setting the limits for the shut down circuit) In RUN mode the oscillator frequency will vary from approximately 30kHz when VCSD is 5V (maximum load) to 55kHz when VCSD is 0V (no load). The result of this is that if a lighter load, such as a single 35W lamp, is connected to a 100W convertor, the frequency will shift upwards so that the output voltage falls below the maximum that is desirable for the lamp. This provides sufficient compensation for the load to ensure that the lamp voltage will always be within acceptable limits but does not require a complicated regulation scheme involving feedback from the output. An additional internal current source has been included to discharge the external capacitor. This will provide approximately 10% ripple at twice the line frequency if CSD is 100nF. The advantage of this is that during the line voltage half cycle the oscillator frequency will vary by several kHz thus spreading the EMI conducted and radiated emissions over a range of frequencies and avoiding high amplitude peaks at particular frequencies. In this way the filter components used may be similar to those used in a common bipolar self- oscillating system. Figure 5, Voltage Compensation Circuit CS CSD AV > 13 150K 12K Figure 6, VS voltage and CSD voltage. In the above trace it can be seen that a leading edge phase cut (triac) dimmer is connected at close to maximum brightness. There is a short delay at the beginning of each half cycle before the AC line voltage is switched to the convertor. Dimming increases the ripple in the CSD voltage and gives more modulation. This is an inherent effect that causes no system problems. The startup sequence of the CSD pin can be seen from the point where VCC increases above the UVLO+ threshold. Figure 7, Startup sequence of CSD. |
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Similar Description - IR2161S |
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