SN74AUC1G80

SINGLE POSITIVEEDGETRIGGERED DTYPE FLIPFLOP

SCES388H − MARCH 2002 − REVISED FEBRUARY 2004

4

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

VCC = 0.8 V

VCC = 1.2 V

± 0.1 V

VCC = 1.5 V

± 0.1 V

VCC = 1.8 V

± 0.15 V

VCC = 2.5 V

± 0.2 V

UNIT

TYP

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

50

200

225

250

275

MHz

tw

Pulse duration, CLK high or low

4.6

1.7

1.7

1.7

1.7

ns

tsu

Setup time before CLK

↑, Data high or low

1.6

1.1

0.8

0.6

0.5

ns

th

Hold time, data after CLK

↑

0

0

0.1

0.1

0.1

ns

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 0.8 V

VCC = 1.2 V

± 0.1 V

VCC = 1.5 V

± 0.1 V

VCC = 1.8 V

± 0.15 V

VCC = 2.5 V

± 0.2 V

UNIT

PARAMETER

(INPUT)

(OUTPUT)

TYP

MIN

MAX

MIN

MAX

MIN

TYP

MAX

MIN

MAX

UNIT

fmax

50

200

225

250

275

MHz

tpd

CLK

Q

5

1

3.9

0.8

2.5

0.3

1

1.9

0.3

1.3

ns

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 1.8 V

± 0.15 V

VCC = 2.5 V

± 0.2 V

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

UNIT

fmax

250

275

ns

tpd

CLK

Q

0.8

1.5

2.4

0.6

1.8

ns

PARAMETER

TEST

VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V

UNIT

PARAMETER

TEST

CONDITIONS

TYP

TYP

TYP

TYP

TYP

UNIT

Cpd

Power dissipation

capacitance

f = 10 MHz

18

18

18

18.5

20.5

pF