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IN74AC574 Datasheet(PDF) 4 Page - Integral Corp.

Part No. IN74AC574
Description  Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS
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Manufacturer  INTEGRAL [Integral Corp.]
Direct Link  http://www.iksemi.com/
Logo INTEGRAL - Integral Corp.

IN74AC574 Datasheet(HTML) 4 Page - Integral Corp.

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IN74AC574
469
AC ELECTRICAL CHARACTERISTICS(C
L=50pF, Input tr=tf=3.0 ns)
VCC
*
Guaranteed Limits
Symbol
Parameter
V
25
°C-40°C to
85
°C
Unit
Min
Max
Min
Max
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figure 1)
3.3
5.0
75
95
60
85
MHz
tPLH
Propagation Delay, Clock to Q (Figure 1)
3.3
5.0
3.5
2.0
13.5
9.5
3.5
2.0
15
11
ns
tPHL
Propagation Delay, Clock to Q (Figure 1)
3.3
5.0
3.5
2.0
12
8.5
3.5
2.0
13.5
9.5
ns
tPZH
Propagation Delay, Output Enable to Q
(Figure 2)
3.3
5.0
2.5
2.0
11
8.5
2.5
2.0
12
9.0
ns
tPZL
Propagation Delay, Output Enable to Q
(Figure 2)
3.3
5.0
3.0
1.5
10.5
8.0
3.5
2.0
11.5
9.0
ns
tPHZ
Propagation Delay, Output Enable to Q
(Figure 2)
3.3
5.0
4.0
2.0
12
9.5
4.5
2.0
13
10.5
ns
tPLZ
Propagation Delay, Output Enable to Q
(Figure 2)
3.3
5.0
2.0
1.5
9.0
7.5
2.5
1.5
10
8.5
ns
CIN
Maximum Input Capacitance
5.0
5.0
5.0
pF
Typical @25
°C,V
CC=5.0 V
CPD
Power Dissipation Capacitance
25
pF
*Voltage Range 3.3 V is 3.3 V
±0.3 V
Voltage Range 5.0 V is 5.0 V
±0.5 V
TIMING REQUIREMENTS (C
L=50pF, Input tr=tf=3.0 ns)
VCC*
Guaranteed Limit
Symbol
Parameter
V
25
°C-40°C to 85°C
Unit
tSU
Minimum Setup Time, Data to Clock (Figure
3)
3.3
5.0
2.5
1.5
3.0
2.0
ns
th
Minimum Hold Time, Clock to Data (Figure
3)
3.3
5.0
1.5
1.5
1.5
1.5
ns
tw
Minimum Pulse Width, Clcok (Figure 1)
3.3
5.0
6.0
4.0
7.0
5.0
ns
*Voltage Range 3.3 V is 3.3 V
±0.3 V
Voltage Range 5.0 V is 5.0 V
±0.5 V


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