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TMS28F004AZB80BDCDL Datasheet(PDF) 51 Page - Texas Instruments |
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TMS28F004AZB80BDCDL Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 80 page  timing requirements for TMS28F004AMy and TMS28F400AMy write/erase operations — E-controlled writes ALT ’28F004AMy 60 ’28F400AMy 60 ’28F004AMy 70 ’28F400AMy70 28F004AMy 80 ’28F400AMy80 ALT. SYMBOL 3.3-V VCC RANGE 5-V VCC RANGE 3.3-V VCC RANGE 5-V VCC RANGE 3.3-V VCC RANGE 5-V VCC RANGE UNIT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tc( E ) Cycle time, write tAVAV 110 60 130 70 150 80 ns tc(E)OP Cycle time, duration of programming operation tEHQV1 6 6 6 6 6 6 µs tc(E)ERB Cycle time, erase operation (boot block) tEHQV2 0.3 0.3 0.3 0.3 0.3 0.3 s tc(E)ERP Cycle time, erase operation (parameter block) tEHQV3 0.3 0.3 0.3 0.3 0.3 0.3 s tc(E)ERM Cycle time, erase operation (main block) tEHQV4 0.6 0.6 0.6 0.6 0.6 0.6 s td(RPR) Delay time, boot-block relock tPHBR 200 100 200 100 200 100 ns th(A) Hold time, A0 – A17 (see Note 15) tEHAX 0 0 0 0 0 0 ns th(D) Hold time, DQ valid tEHDX 0 0 0 0 0 0 ns th( W ) Hold time, W tEHWH 0 0 0 0 0 0 ns th (VPP) Hold time, VPP from valid status-register bit tQVVL 0 0 0 0 0 0 ns th(RP) Hold time, RP at VHH from valid status-register bit tQVPH 0 0 0 0 0 0 ns tsu(A) Setup time, A0 – A17 (see Note 15) tAVEH 90 50 105 50 120 50 ns tsu(D) Setup time, DQ tDVEH 90 50 105 50 120 50 ns tsu( W ) Setup time, W before write operation tWLEL 0 0 0 0 0 0 ns tsu(RP) Setup time, RP at VHH to E going high tPHHEH 200 100 200 100 200 100 ns tsu( VPP)2 Setup time, VPP to E going high tVPEH 200 100 200 100 200 100 ns tw(E) Pulse duration, E low tELEH 90 50 105 50 120 50 ns tw( EH) Pulse duration, E high tEHEL 20 10 25 20 30 30 ns trec(RPHE) Recovery time, RP high to E going low tPHEL 800 450 800 450 800 450 ns NOTE 15: A–1 – A17 for byte-wide |
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