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TMS28F004AZB60BDBJL Datasheet(PDF) 14 Page - Texas Instruments

Part No. TMS28F004AZB60BDBJL
Description  524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TMS28F004AZB60BDBJL Datasheet(HTML) 14 Page - Texas Instruments

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TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
D read array
The array level is read by entering the command code FFh on DQ0 – DQ7. Control pins E and G must be at a
logic-low level ( VIL) and W and RP must be at a logic-high level (VIH) to read data from the array. Data is
available on DQ0 – DQ15 (word-wide mode) or DQ0 – DQ7 (byte-wide mode ). Any valid address within any
of the blocks selects that block and allows data to be read from the block.
D read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0 – DQ7. Two bus cycles are
required for this operation: the first to enter the command code and a second to read the device-equivalent
code. Control pins E and G must be at a logic-low level ( VIL) and W and RP must be at a logic-high level
(VIH). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on
DQ0 – DQ7 with A0 at a logic-low level ( VIL). The device-equivalent code is obtained when A0 is set to a
logic-high level ( VIH). Alternatively, the manufacturer- and device-equivalent codes can be read by applying
VID (nominally 12 V) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are
“don’t cares” (see Table 4, Table 6, Table 7, Table 8).
D read status register
The status register is read by entering the command code 70h on DQ0 – DQ7. Control pins E and G must be
at a logic-low level ( VIL) and W and RP must be at a logic-high level (VIH). Two bus cycles are required for
this operation: one to enter the command code and a second to read the status register. In a given read
cycle, status register contents are updated on the falling edge of E or G, whichever occurs last within the
cycle.
programming operations
There are two CSM commands for programming: program setup and alternate program setup
(see Table 3 ). After the desired command code is entered, the WSM takes over and correctly sequences the
device to complete the program operation. During this time, the CSM responds only to status reads until the
program operation has been completed, after which all commands to the CSM become valid again. Once a
program command has been issued, the WSM normally cannot be interrupted until the program algorithm is
completed (see Figure 3 and Figure 4).
Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain in
the appropriate VPP voltage range, as shown in the recommended operating conditions table. Different
combinations of RP, WP, and VPP pin voltage levels ensure that data in certain blocks are secure, and, therefore,
cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and compared during a
program operation. If 1s are programmed, the memory cell contents do not change and no error occurs.
A program-setup command can be aborted by writing FFh ( in byte-wide mode) or FFFFh ( in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.
When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated,
all commands to the CSM become valid again.


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