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TMS28F004AZB60BDBJL Datasheet(PDF) 10 Page - Texas Instruments

Part No. TMS28F004AZB60BDBJL
Description  524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TMS28F004AZB60BDBJL Datasheet(HTML) 10 Page - Texas Instruments

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TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
command definitions (continued)
Table 4. Command Definitions
BUS
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
CYCLES
REQUIRED
OPERATION
ADDRESS
CSM
INPUT
OPERATION
ADDRESS
DATA
IN / OUT
Read Operations
Read Array
1
Write
X
FFh
Read
X
Data Out
Read Algorithm-Selection Code
2
Write
X
90h
Read
A0
M/D
Read-Status Register
2
Write
X
70h
Read
X
SRB
Clear-Status Register
1
Write
X
50h
Program Mode
Program Setup / Program
(byte / word)
2
Write
PA
40h or 10h
Write
PA
PD
Erase Operations
Block-Erase Setup/
Block-Erase Confirm
2
Write
BEA
20h
Write
BEA
D0h
Erase Suspend/
Erase Resume
2
Write
X
B0h
Write
X
D0h
Legend:
BEA
Block-erase address. Any address selected within a block selects that block for erase.
M / D
Manufacturer-equivalent/ device-equivalent code
PA
Address to be programmed
PD
Data to be programmed at PA
SRB
Status-register data byte that can be found on DQ0 – DQ7
X
Don’t care
status register
The status register allows the user to determine whether the state of a program/erase operation is pending or
complete. The status register is monitored by writing a read-status command to the CSM and reading the
resulting status code on I/O pins DQ0 – DQ7. This is valid for operation in either the byte- or word-wide mode.
When writing to the CSM in word-wide mode, the high order I/O pins (DQ8 – DQ15) can be set to any valid 2-state
level. When reading the status bits during a word-wide read operation, the high order I/Os (DQ8 – DQ15) are
set to 00h internally, so the user needs to interpret only the low order I/O pins (D0 – DQ7).
After a read-status command has been given, the data appearing on DQ0 – DQ7 remains as status register data
until a new command is issued to the CSM. To return the device to other modes of operation, a new command
must be issued to the CSM.
Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching the data prevents errors from occurring if the register input
change during a status-register read. To ensure that the status-register output contains updated status data,
E or G must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSM status. Table 5 defines the status
register bits and their functions.


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