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TMS28F004AZB60CDBJL Datasheet(PDF) 15 Page - Texas Instruments

Part No. TMS28F004AZB60CDBJL
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Maker  TI [Texas Instruments]
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TMS28F004AZB60CDBJL Datasheet(HTML) 15 Page - Texas Instruments

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TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
HOUSTON, TEXAS 77251–1443
erase operations
There are two erase operations that can be performed by the TMS28F004Axy and TMS28F400Axy devices:
block erase and erase suspend / erase resume. An erase operation must be used to initialize all bits in an array
block to 1s. After block-erase confirm is issued, the CSM responds only to status reads or erase-suspend
commands until the WSM completes its task.
D block erasure
Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is
accomplished only by blocks; data at single address locations within the array cannot be erased individually.
The block to be erased is selected by using any valid address within that block. Note that different
combinations of RP, WP and VPP pin voltage levels ensure that data in certain blocks are secure and,
therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a command
sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A
two-command erase sequence protects against accidental erasure of memory contents.
Erase setup and confirm commands are latched on the rising edge of E or W, whichever occurs first. Block
addresses are latched during the block-erase-confirm command on the rising edge of E or W (see Figure 14
and Figure 15). When the block-erase-confirm command is complete, the WSM automatically executes a
sequence of events to complete the block erasure. During this sequence, the block is programmed with
logic 0s, data is verified, all bits in the block are erased, and finally, verification is performed to ensure that all
bits are correctly erased. Monitoring of the erase operation is possible through the status register (see the
subsection, “read status register”).
D erase suspend/erase resume
During the execution of an erase operation, the erase-suspend command (B0h ) can be entered to direct the
WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to
respond only to the read-array, read-status-register, and erase-resume commands. During the
erase-suspend operation, array data must be read from a block other than the one being erased. To resume
the erase operation, an erase-resume command (D0h ) must be issued to cause the CSM to clear the
suspend state previously set (see Figure 5 and Figure 6).
automatic power-saving mode
Substantial power savings are realized during periods when the array is not being read and the device is in the
active mode. During this time, the device switches to the automatic power-saving (APS) mode. When the device
switches to this mode, ICC is typically reduced from 40 mA to 1 mA (IOUT = 0 mA). The low level of power is
maintained until another read operation is initiated. In this mode, the I/O pins retain the data from the last
memory address read until a new address is read. This mode is entered automatically if no address or control
pins toggle within approximately a 200-ns time-out period. At least one transition on E must occur after power
up to activate this mode.
reset / deep power-down mode
Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device
circuitry. When RP is at a CMOS logic-low level of 0.0 V
± 0.2 V, a much lower ICC value or power is achievable.
This is important in portable applications where extended battery life is of major concern.
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a
minimum of td(RP) is required before data is valid, and a minimum of trec(RPHE) and trec(RPHW) in deep
power-down mode is required before data input to the CSM can be recognized. With RP at ground, the WSM
is reset and the status register is cleared, effectively eliminating accidental programming to the array during
system reset. After restoration of power, the device does not recognize any operation command until RP is
returned to a VIH or VHH level.

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