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TMS28F004AZB60CDBJL Datasheet(PDF) 13 Page - Texas Instruments

Part No. TMS28F004AZB60CDBJL
Description  524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TMS28F004AZB60CDBJL Datasheet(HTML) 13 Page - Texas Instruments

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TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
byte-wide or word-wide mode selection (continued)
Table 8. Operation Modes for TMS28F004Axy
MODE
WP
E
G
RP
W
A9
A0
VPP
DQ0 – DQ7
Read
X
VIL
VIL
VIH
VIH
X
X
X
Data out
X
VIL
VIL
VIH
VIH
VID
VIL
X
Manufacturer-equivalent code 89h
Device equivalent code 78h (top boot block)
Algorithm-selection mode
Device-equivalent code 78h (top boot block)
Algorithm-selection mode
X
VIL
VIL
VIH
VIH
VID
VIH
X
Device-equivalent code 79h (bottom boot
block)
Output disable
X
VIL
VIH
VIH
VIH
X
X
X
Hi-Z
Standby
X
VIH
X
VIH
X
X
X
X
Hi-Z
Reset / deep power down
X
X
X
VIL
X
X
X
X
Hi-Z
Write (see Note 3)
VIL
or
VIH
VIL
VIH
VIH
or
VHH
VIL
X
X
VPPL
or
VPPH
Data in
NOTES:
2. X = don’t care
3. When writing commands to the ’28F004Axy, VPP must be in the appropriate VPP voltage range (as shown in the recommended
operating conditions table) for block-erase or program commands to be executed. Also, depending on the combination of RP and
WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for a list of the combinations).
command-state machine (CSM) operations
The CSM decodes instructions for read, read algorithm-selection code, read status register, clear status
register, program, erase, erase-suspend, and erase-resume. The 8-bit command code is input to the device on
DQ0 – DQ7 (see Table 3 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a
program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences
and the CSM responds only to status reads.
During an erase cycle, the CSM responds to status read and erase-suspend commands. When the WSM has
completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when VPP is within its correct voltage range.
For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the VPP status (SB3), the program status bit (SB4), and the erase status bit
(SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor to
clear these status bits and synchronize to internal operations. When the status bits are cleared, the device
returns to the read array mode.


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