ZL50050GAG2 datasheet(76/94 Pages) ZARLINK

Part #	ZL50050GAG2

Description	8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs

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Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

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ZL50050

Data Sheet

76

Zarlink Semiconductor Inc.

14.14

Memory BIST Register

Address 014DH.

The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to

start MBIST: the first with only bit 12 (LV_TM) set HIGH (i.e., 1000h); the second with bit 12 maintained HIGH but

with the required start bit(s) also set HIGH.

The MBISTR register is configured as follows:

Bit

Name

Reset

Value

Description

15:13

Reserved

0

Reserved

Must be set to 0 for normal operation

12

LV_TM

0

MBIST Test Enable

Set HIGH to enable MBIST mode.

Set LOW for normal operation.

11

BISTSDB

0

Backplane Data Memory Start BIST Sequence

Sequence enabled on LOW to HIGH transition.

10

BISTCDB

0

Backplane Data Memory BIST Sequence Completed (Read-only)

This bit must be polled - when HIGH, indicates completion of Backplane Data

Memory BIST sequence.

9BISTPDB

0

Backplane Data Memory Pass/Fail Bit (Read-only)

This bit indicates the Pass/Fail status following completion of the Backplane

Data Memory BIST sequence (indicated by assertion of BISTCDB).

A HIGH indicates Pass, a LOW indicates Fail.

8BISTSDL

0

Local Data Memory Start BIST Sequence

Sequence enabled on LOW to HIGH transition.

7

BISTCDL

0

Local Data Memory BIST Sequence Completed (Read-only)

This bit must be polled - when HIGH, indicates completion of Local Data

Memory BIST sequence.

6BISTPDL

0

Local Data Memory Pass/Fail Bit (Read-only)

This bit indicates the Pass/Fail status following completion of the Local Data

Memory BIST sequence (indicated by assertion of BISTCDL).

A HIGH indicates Pass, a LOW indicates Fail.

5BISTSCB

0

Backplane Connection Memory Start BIST Sequence

Sequence enabled on LOW to HIGH transition.

4

BISTCCB

0

Backplane Connection Memory BIST Sequence Completed (Read-only)

This bit must be polled - when HIGH, indicates completion of Backplane

Connection Memory BIST sequence.

3BISTPCB

0

Backplane Connection Memory Pass/Fail Bit (Read-only)

This bit indicates the Pass/Fail status following completion of the Backplane

Connection Memory BIST sequence (indicated by assertion of BISTCCB).

A HIGH indicates Pass, a LOW indicates Fail.

Table 54 - Memory BIST Register (MBISTR) Bits

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ZL50050GAG2 Datasheet(PDF) 76 Page - Zarlink Semiconductor Inc

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