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ZL50050 Datasheet(PDF) 87 Page - Zarlink Semiconductor Inc |
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ZL50050 Datasheet(HTML) 87 Page - Zarlink Semiconductor Inc |
87 / 94 page ZL50050 Data Sheet 87 Zarlink Semiconductor Inc. Figure 28 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) CK_int * L/BSTi0-15 L/BSTo0-15 tIDS8 8.192 Mbps 8.192 Mbps Note *: CK_int is the internal clock signal of 131.072 MHz FP8i C8i tIDS4 tIDS2 tSIH8 tSIS8 tSIH4 tSIS4 tSIH2 tSIS2 tSOD2 tSOD4 tSOD8 L/BSTo0-15 4.096 Mbps L/BSTo0-15 2.048 Mbps L/BSTi0-15 4.096 Mbps L/BSTi0-15 2.048 Mbps Bit0 Ch0 Bit1 Ch0 Bit0 Ch0 Bit1 Ch0 Bit7 Ch31 Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit0 Ch0 Bit1 Ch0 Bit7 Ch31 Bit2 Ch0 Bit3 Ch0 Bit1 Ch0 Bit0 Ch0 Bit7 Ch63 Bit6 Ch127 Bit7 Ch127 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 1 2 7 3 4 5 6 6 0 CK_int * FP8o C8o tOFBOS |
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Similar Description - ZL50050 |
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