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DS2065W Datasheet(PDF) 6 Page - Maxim Integrated Products

Part No. DS2065W
Description  3.3V Single-Piece 8Mb Nonvolatile SRAM
Download  12 Pages
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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DS2065W Datasheet(HTML) 6 Page - Maxim Integrated Products

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DS2065W 3.3V Single-Piece 8Mb
Nonvolatile SRAM
6
_____________________________________________________________________
Power-Down/Power-Up Condition
tDR
tPU
tF
tPD
tRPU
tRPD
SLEWS WITH
VCC
tR
VOL
VIH
VOL
tREC
VCC
VTP
~2.5V
CE,
WE
RST
BACKUP CURRENT
SUPPLIED FROM
LITHIUM BATTERY
(SEE NOTES 1, 7.)
Note 1:
RST is an open-drain output and cannot source current. An external pullup resistor should be connected to this pin to real-
ize a logic-high level.
Note 2:
These parameters are sampled with a 5pF load and are not 100% tested.
Note 3:
tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of
CE or WE going high.
Note 4:
tWR1 and tDH1 are measured from WE going high.
Note 5:
tWR2 and tDH2 are measured from CE going high.
Note 6:
tDS is measured from the earlier of CE or WE going high.
Note 7:
In a power-down condition, the voltage on any pin cannot exceed the voltage on VCC.
Note 8:
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the
user. Minimum expected data-retention time is based on a maximum of two +230°C convection solder reflow exposures,
followed by a fully charged cell. Full charge occurs with the initial application of VCC for a minimum of 96 hours. This para-
meter is assured by component selection, process control, and design. It is not measured directly in production testing.
Note 9:
WE is high for a read cycle.
Note 10: OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
Note 11: If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-
impedance state during this period.
Note 12: If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-
impedance state during this period.
Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain
in a high-impedance state during this period.
Note 14: DS2065W BGA modules are recognized by Underwriters Laboratory (UL) under file E99151.


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