9

®

OPA641

Many demanding high-speed applications such as

ADC/DAC buffers require op amps with low wideband

output impedance. For example, low output impedance is

essential when driving the signal-dependent capacitances at

the inputs of flash A/D converters. As shown in Figure 3,

the OPA641 maintains very low closed-loop output imped-

ance over frequency. Closed-loop output impedance in-

creases with frequency since loop gain is decreasing with

frequency.

THERMAL CONSIDERATIONS

The OPA641 does not require a heat sink for operation in

most environments. At extreme temperatures and under full

load conditions a heat sink may be necessary.

The internal power dissipation is given by the equation

tion and P

to the load. (For

±V

= 10V x 24mA =

240mW, max). For the case where the amplifier is driving a

the output transistor, and not the load, that determines the

power dissipated in the output stage.

The short-circuit condition represents the maximum amount

of internal power dissipation that can be generated. The

variation of output current with temperature is shown in the

Typical Performance Curves.

CAPACITIVE LOADS

The OPA641’s output stage has been optimized to drive low

resistive loads. Capacitive loads, however, will decrease the

amplifier’s phase margin which may cause high frequency

peaking or oscillations. Capacitive loads greater than 5pF

should be buffered by connecting a small resistance, usually

5

Ω to 25Ω, in series with the output as shown in Figure 4.

This is particularly important when driving high capacitance

loads such as flash A/D converters.

In general, capacitive loads should be minimized for opti-

mum high frequency performance. Coax lines can be driven

if the cable is properly terminated. The capacitance of coax

cable (29pF/foot for RG-58) will not load the amplifier

when the coaxial cable or transmission line is terminated in

its characteristic impedance.

COMPENSATION

The OPA641 is internally compensated and is stable in unity

gain with a phase margin of approximately 60

°. However,

the unity gain buffer is the most demanding circuit configu-

ration for loop stability and oscillations are most likely to

occur in this gain. If possible, use the device in a noise gain

of two or greater to improve phase margin and reduce the

susceptibility to oscillation. (Note that, from a stability

standpoint, an inverting gain of –1V/V is equivalent to a

noise gain of 2.) Gain and phase response for other gains are

shown in the Typical Performance Curves.

The high-frequency response of the OPA641 in a good

layout is very flat with frequency. However, some circuit

configurations such as those where large feedback resis-

tances are used, can produce high-frequency gain peaking.

This peaking can be minimized by connecting a small

capacitor in parallel with the feedback resistor. This capaci-

tor compensates for the closed-loop, high frequency, transfer

function zero that results from the time constant formed by

the input capacitance of the amplifier (typically 2pF after PC

board mounting), and the input and feedback resistors. The

selected compensation capacitor may be a trimmer, a fixed

capacitor, or a planned PC board capacitance. The capaci-

tance value is strongly dependent on circuit layout and

closed-loop gain. Using small resistor values will preserve

the phase margin and avoid peaking by keeping the break

frequency of this zero sufficiently high. When high closed-

loop gains are required, a three-resistor attenuator (tee net-

work) is recommended to avoid using large value resistors

with large time constants.

SETTLING TIME

Settling time is defined as the total time required, from the

input signal step, for the output to settle to within the

specified error band around the final value. This error band is

expressed as a percentage of the value of the output transition,

a 2V step. Thus, settling time to 0.01% requires an error band

of

±200µV centered around the final value of 2V.

FIGURE 3. Small-Signal Output Impedance vs Frequency.

FIGURE 4. Driving Capacitive Loads.

OPA641

C

L

R

L

R

S

(R

100

10.0

1.0

0.1

0.01

0.001

10k

Frequency (Hz)

100k

1M

10M

100M

A