8

OPA641

®

the end of the datasheet. A longer feedback path than this

will decrease the realized bandwidth substantially.

6) Due to the extremely high bandwidth of the OPA641, the

SOIC package is strongly recommended due its low para-

sitic impedance. The parasitic impedance in the PDIP and

CERDIP packages causes the OPA641 to experience about

5dB of gain peaking in unity-gain configurations. This is

compared with virtually no gain peaking in the SOIC pack-

age in unity-gain. The gain peaking in the PDIP and CERDIP

packages is minimized in gains of 4 or greater, however.

Surface mount components (chip resistors, capacitors, etc.)

also have low lead inductance and are therefore strongly

recommended.

7) Avoid overloading the output. Remember that output

current must be provided by the amplifier to drive its own

feedback network as well as to drive its load. Lowest

distortion is achieved with high impedance loads.

8) Don’t forget that these amplifiers use

±5V supplies.

Although they will operate perfectly well with +5V and

–5.2V, use of

±15V supplies will destroy the part.

9) Standard commercial test equipment has not been de-

signed to test devices in the OPA641’s speed range. Bench-

top op amp testers and ATE systems will require a special

test head to successfully test these amplifiers.

10) Terminate transmission line loads. Unterminated lines,

such as coaxial cable, can appear to the amplifier to be a

capacitive or inductive load. By terminating a transmission

line with its characteristic impedance, the amplifier’s load

then appears purely resistive.

11) Plug-in prototype boards and wire-wrap boards will not

be satisfactory. A clean layout using RF techniques is

essential; there are no shortcuts.

OFFSET VOLTAGE ADJUSTMENT

If additional offset adjustment is needed, the circuit in

Figure 1 can be used without degrading offset drift with

temperature. Avoid external adjustment whenever possible

since extraneous noise, such as power supply noise, can be

inadvertently coupled into the amplifier’s inverting input

terminal. Remember that additional offset errors can be

created by the amplifier’s input bias currents. Whenever

possible, match the impedance seen by both inputs as is

the amplifier’s offset current.

INPUT PROTECTION

Static damage has been well recognized for MOSFET de-

vices, but any semiconductor device deserves protection

from this potentially damaging source. The OPA641 incor-

porates on-chip ESD protection diodes as shown in Figure 2.

This eliminates the need for the user to add external protec-

tion diodes, which can add capacitance and degrade AC

performance.

All pins on the OPA641 are internally protected from ESD

NOTE: (1) R

bias currents.

FIGURE 1. Offset Voltage Trim.

by means of a pair of back-to-back reverse-biased diodes to

either power supply as shown. These diodes will begin to

conduct when the input voltage exceeds either power supply

by about 0.7V. This situation can occur with loss of the

amplifier’s power supplies while a signal source is still

present. The diodes can typically withstand a continuous

current of 30mA without destruction. To insure long term

reliability, however, diode current should be externally lim-

ited to 10mA or so whenever possible.

The OPA641 utilizes a fine geometry high speed process

that withstands 500V using Human Body Model and 100V

using the Machine Model. However, static damage can

cause subtle changes in amplifier input characteristics with-

out necessarily destroying the device. In precision opera-

tional amplifiers, this may cause a noticeable degradation of

offset voltage and drift. Therefore, static protection is strongly

recommended when handling the OPA641.

OUTPUT DRIVE CAPABILITY

The OPA641 has been optimized to drive 75

Ω and 100Ω

resistive loads. The device can drive 2Vp-p into a 75

Ω load.

This high-output drive capability makes the OPA641 an

ideal choice for a wide range of RF, IF, and video applica-

tions. In many cases, additional buffer amplifiers are un-

needed.

ESD Protection diodes internally

connected to all pins.

FIGURE 2. Internal ESD Protection.

External

Pin

+V

CC

–V

CC

Internal

Circuitry

R

2

OPA641

R

3

R

1

R

Trim

+V

CC

–V

CC

20k

Ω

V

Output Trim Range

+V

CC

to –V

CC

≅

R

Trim

47k

Ω

R

2

R

2

R

Trim

10µF