Electronic Components Datasheet Search |
|
AKD4584 Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
|
AKD4584 Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
10 / 41 page ASAHI KASEI [AKD4584] <KM065800> ’01/11 - 10 - (2) Master Mode (2-1) A/D evaluation using DIT function of AK4584 Using X’tal (X1), PORT4 (DIT) and J6 (TX). Nothing should be connected to J7 (RX), PORT1 (DIR), PORT5 (DIR) and PORT6 (ROM). The bi-phase data is output from TX3. JP6 (EXT) should be short. In normal speed, double speed mode and quad speed mode, JP3 (XTI), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open. JP10 MCLK JP3 XTI JP14 LRCK JP6 EXT JP11 BICK EXT DIR JP15 SDTI ADC DIR EXT DIR • Clock Setting (2-1-1) Select MCKO1 JP5 BCFS JP7 LRFS JP4 MCLK x1 x4 JP1 MCKO M2 M1 x2 x1 (2-1-2) Select MCKO2 JP5 BCFS JP7 LRFS JP4 MCLK x1 x4 JP1 MCKO M2 M1 x2 x1 • SW2 (MODE) setting (See Table 1) Normal speed and double speed are same setting. (1) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down. (2) When DMCK is “H”, MCKO1 output is disabled. H L 123 45 8 67 9 10 |
Similar Part No. - AKD4584 |
|
Similar Description - AKD4584 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |