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AK7750 Datasheet(PDF) 19 Page - Asahi Kasei Microsystems |
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AK7750 Datasheet(HTML) 19 Page - Asahi Kasei Microsystems |
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19 / 77 page  [ASAHI KASEI] [AK7750] [MS0296-E-00] 19 2005/03 2) Reset (AVDD=DVDD=3.0 to 3.6V,Ta=-40 °C to 85°C) Parameter Symbol min typ max Units INIT_RESET note 1) tRST 400 ns CK_RESET tRST 400 ns S_RESET tRST 400 ns note1) At the power-on, it is OK to keep this pin to “L”. “H” transition must be made after the power-on and master clock is full running. 3) Audio Interface (AVDD=DVDD=3.0 to 3.6V,Ta= Ta=-40 °C to 85°C, CL=20pF) Parameter Symbol min typ max Units Slave mode BITCLK frequency fBCLK 48 64 64 fs Delay time from BITCLK" ↑“ to LRCLK note1) tBLRD 40 ns Delay time from LRCLK to BITCLK" ↑" note1) tLRBD 40 ns Delay time from LRCLK to serial data output tLRD 80 ns Delay time from BITCLK to serial data output tBSOD 80 ns Serial data input latch hold time tBSIDS 40 ns Serial data input latch setup time tBSIDH 40 ns Master mode BITCLK frequency fBCLK 64 fs BITCLK duty factor 50 % Delay time from BITCLK" ↑" to LRCLK note1) tBLRD 40 ns Delay time from LRCLK to BITCLK" ↑" note1) tLRBD 40 ns Delay time from LRCLK to serial data output tLRD 80 ns Delay time from BITCLK to serial data output tBSOD 80 ns Serial data input latch hold time tBSIDS 40 ns Serial data input latch setup time tBSIDH 40 ns PCM Interface mode (SF/LF) LRCLK frequency fLRCK 8 48 kHz BITCLK frequency fBCLK 64 fs BITCLK duty factor 50 % Delay time from BITCLK" ↑" to LRCLK note1) tBLRD 40 ns Delay time from LRCLK to BITCLK" ↓" note1) tLRBD 40 ns Delay time from LRCLK to serial data output tLRD 80 ns Delay time from BITCLK to serial data output tBSOD 80 ns Serial data input latch hold time tBSIDS 40 ns Serial data input latch setup time tBSIDH 40 ns LRCLK high level width (SF) tLCKKH 64 fs LRCLK high level width (LF) LRCLK low level width (LF) tLCLKH tLCLKL 300 1200 ns ns Note 1) this value is specified such that LRCLK edge and rising edge of BITCLK never overlap |
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