ASAHI KASEI

[AK4120]

MS0134-E-00

2002/1

- 23 -

SCL

SDA

stop condition

start condition

S

P

Figure 17. START and STOP conditions

SCL FROM

MASTER

acknowledge

DATA

OUTPUT BY

TRANSMITTER

DATA

OUTPUT BY

RECEIVER

1

9

8

START

CONDITION

not acknowledge

clock pulse for

acknowledgement

S

2

Figure 18. Acknowledge on the I

SCL

SDA

data line

stable;

data valid

change

of data

allowed

Figure 19. Bit transfer on the I

Note: Only addresses 00H through 06H are valid write addresses. All others should not be read from or written to.