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CG6258AM Datasheet(PDF) 6 Page - Weida Semiconductor, Inc.

Part No. CG6258AM
Description  4Mb (256K x 16) Pseudo Static RAM
Download  12 Pages
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Manufacturer  WEIDA [Weida Semiconductor, Inc.]
Direct Link  http://www.weida.com.my/website/
Logo WEIDA - Weida Semiconductor, Inc.

CG6258AM Datasheet(HTML) 6 Page - Weida Semiconductor, Inc.

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ADVANCE INFORMATION
CG6258AM
38-XXXXX
Page - 6 - of 12
Switching Characteristics Over the Operating Range[11]
Parameter
Description
70 ns
Unit
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
70
ns
tAA
Address to Data Valid
70
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE LOW and CE2 HIGH to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to LOW Z[12, 14]
5
ns
tHZOE
OE HIGH to High Z[12, 14]
25
ns
tLZCE
CE LOW and CE2 HIGH to Low Z[12, 14]
5
ns
tHZCE
CE HIGH and CE2 LOW to High Z[12, 14]
25
ns
tDBE
BLE / BHE LOW to Data Valid
70
ns
tLZBE
BLE / BHE LOW to Low Z[12, 14]
5
ns
tHZBE
BLE / BHE HIGH to HIGH Z[12, 14]
25
ns
tSK
Address Skew
0
ns
WRITE CYCLE[13]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW and CE2 HIGH to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
45
ns
tBW
BLE / BHE LOW to Write End
60
ns
tSD
Data Set-Up to Write End
45
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High-Z[12, 14]
25
ns
tLZWE
WE HIGH to Low-Z[12, 14]
5
ns
Notes:
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1ns/V, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section..
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the
signal that terminates the write.
14. High-Z and Low-Z parameters are characterized and are not 100% tested.


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