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LMX2332LTMX Datasheet(PDF) 20 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. LMX2332LTMX
Description  PLLatinumTM Low Power Dual Frequency Synthesizer for RF Personal Communications
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LMX2332LTMX Datasheet(HTML) 20 Page - National Semiconductor (TI)

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Application Information (Continued)
margin. This implies that another resistor of equal value to
R2 will need to be switched in parallel with R2 during the
initial lock period. We must also insure that the magnitude of
the open loop gain, H(s)G(s) is equal to zero at wp’ = 2wp.
K
vco,Kφ, N, or the net product of these terms can be
changed by a factor of 4, to counteract the w
2 term present
in the denominator of
Equation (2) and Equation (3). The K
φ
term was chosen to complete the transformation because it
can readily be switched between 1X and 4X values. This is
accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX233XL PLL is shown in
Figure 5.
When a new frequency is loaded, and the RF Icp
o bit is set
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter com-
ponent values for the normal steady state considerations.
The device configuration ensures that as long as a second
identical damping resistor is wired in appropriately, the loop
will lock faster without any additional stability considerations
to account for. Once locked on the correct frequency, the
user can return the PLL to standard low noise operation by
sending a MICROWIRE instruction with the RF Icp
o bit set
low. This transition does not affect the charge on the loop
filter capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change be-
tween Fastlock and standard mode.
01280617
FIGURE 4. Open Loop Response Bode Plot
01280618
FIGURE 5. Fastlock PLL Architecture
www.national.com
20


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