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DLO31F-5.5MD4 Datasheet(PDF) 2 Page - Data Delay Devices, Inc. |
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DLO31F-5.5MD4 Datasheet(HTML) 2 Page - Data Delay Devices, Inc. |
2 / 4 page DLO31F Doc #98001 DATA DELAY DEVICES, INC. 2 3/17/98 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com APPLICATION NOTES THERMAL STABILITY The delay line used internally to develop the clock signals in the DLO31F has a thermal coefficient of 100ppm/C. For low frequency units, this is also the thermal coefficient of the output frequency. For higher frequency units, however, other internal effects must be considered, and the actual thermal coefficient may be somewhat higher. POWER SUPPLY BYPASSING The DLO31F relies on a stable power supply to produce a repeatable frequency within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended. A wide VCC trace and a clean ground plane should be used. DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage VCC -0.3 7.0 V Input Pin Voltage VIN -0.3 VDD+0.3 V Storage Temperature TSTRG -55 150 C Lead Temperature TLEAD 300 C 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES High Level Output Voltage VOH 2.5 3.4 V VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX Low Level Output Voltage VOL 0.35 0.5 V VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX High Level Output Current IOH -1.0 mA Low Level Output Current IOL 20.0 mA High Level Input Voltage VIH 2.0 V Low Level Input Voltage VIL 0.8 V Input Clamp Voltage VIK -1.2 V VCC = MIN, II = IIK Input Current at Maximum Input Voltage IIHH 0.1 mA VCC = MAX, VI = 7.0V High Level Input Current IIH 20 µA VCC = MAX, VI = 2.7V Low Level Input Current IIL -0.6 mA VCC = MAX, VI = 0.5V Short-circuit Output Current IOS -60 -150 mA VCC = MAX Output High Fan-out 25 Unit Output Low Fan-out 12.5 Load TABLE 3: AC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX UNITS Enable to Clock On (Inherent Delay) tEO 3.5 5.5 7.0 ns Disable to Clock Off tDO 3.5 5.5 7.0 ns Clock Skew tCS 2.5 3.5 4.5 ns Gate Recovery Time tGR 50 % of Clock Period |
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