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XC9101C69AKR Datasheet(PDF) 10 Page - Torex Semiconductor

Part # XC9101C69AKR
Description  PWM Controlled Step-Up DC/DC Controllers
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Manufacturer  TOREX [Torex Semiconductor]
Direct Link  http://www.torex.co.jp
Logo TOREX - Torex Semiconductor

XC9101C69AKR Datasheet(HTML) 10 Page - Torex Semiconductor

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XC9101Series
396
4
Output signal to EXT pin
PWM/PFM switching signal
D
CLK
Q
PWM/PFM switching signal
CLK sync signal
Limiter signal
/RESET
■Operational Explanation
Step-up DC/DC converter controllers of the XC9101 series carry out pulse width modulation (PWM) according to the multiple feedback signals
of the output voltage and coil current.
The internal circuits consist of different blocks that operate at VIN or the stabilized power (2.0 V) of the internal regulator. The output setting
voltage of the type C controller and the FB pin voltage (Vref = 0.9 V) of type D controller have been adjusted and set by laser-trimming.
<Clock>
With regard to clock pulses, a capacitor and resistor connected to the CLK pin generate ramp waveforms whose top and bottom are 0.7V and
0.15V, respectively. The frequency can be set within a range of 100 to 600 kHz externally (refer to the "Functional Settings" section for further
information). The clock pulses are processed to generate a signal used for synchronizing internal sequence circuits.
<Verr amplifier>
The Verr amplifier is designed to monitor the output voltage. A fraction of the voltage applied to internal resistors R1, R2 in the case of a type C
controller, and the voltage at the FB pin in the case of a type D controller, are fed back and compared with the reference voltage. In response to
feedback of a voltage lower than the reference voltage, the output voltage of the Verr amplifier increases.
The output of the Verr amplifier enters the mixer via resistor (RVerr). This signal works as a pulse width control signal during PWM operations.
By connecting an external capacitor and resistor through the CE/GAIN pin, it is possible to set the gain and frequency characteristics of Verr
amplifier signals (refer to the "Functional Settings" section for further information).
<Ierr amplifier>
The Ierr amplifier monitors the coil current. The potential difference between the VIN and Isen pins is sampled at each switching operation.
Then the potential difference is amplified or held, as necessary, and input to the mixer. The Ierr amplifier outputs a signal ensuring that the
greater the potential difference between the VIN and Isen pins, the smaller the switching current. The gain and frequency characteristics of this
amplifier are fixed internally.
<Mixer and PWM>
The mixer modulates the signal sent from Verr by the signal from Ierr. The modulated signal enters the PWM comparator for comparison with
the sawtooth pulses generated at the CLK pin. If the signal is greater than the sawtooth waveforms, a signal is sent to the output circuit to turn
on the external switch.
<Current Limiter>
The current flowing through the coil is monitored by the limiter comparator via the VIN and Isen pins. The limiter comparator outputs a signal
when the potential difference between the VIN and Isen pins reaches about 150 mV or more. This signal is converted to a logic signal and
handled as a DFF reset signal for the internal limiter circuit. When a reset signal is input, a signal is output immediately at the EXT pin to turn off
the MOS switch. When the limiter comparator sends a signal to enable data acceptance, a signal to turn on the MOS switch is output at the
next clock pulse. If at this time the potential difference between the VIN and Isen pins is large, operation is repeated to turn off the MOS switch
again. DFF operates in synchronization with the clock signal of the CLK pin.
<Soft Start>
The soft start function is made available by attaching a capacitor and resistor to the CE/SS pin. The Vref voltage applied to the Verr amplifier is
restricted by the start-up voltage of the CE/SS pin. This ensures that the Verr amplifier operates with its two inputs in balance, thereby
preventing the ON-TIME signal from becoming stronger than necessary. Consequently, soft start time needs to be set sufficiently longer than
the time set to CLK. The start-up time of the CE/SS pin equals the time set for soft start (refer to the "Functional Settings" section for further
information).
The soft start function operates when the voltage at the CE/SS pin is between 0V to 1.55V. If the voltage at the CE/SS pin doesn't start from 0V
but from a mid level voltage when the power is switched on, the soft start function will become ineffective and the possibilities of large rush
currents and ripple voltages occuring will be increased.
04S_01XC9101/9102新規 02.09.12 14:38 ページ 396


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