Electronic Components Datasheet Search |
|
PDU18F-1C5 Datasheet(PDF) 1 Page - Data Delay Devices, Inc. |
|
PDU18F-1C5 Datasheet(HTML) 1 Page - Data Delay Devices, Inc. |
1 / 5 page PDU18F 8-BIT PROGRAMMABLE DELAY LINE (SERIES PDU18F) FEATURES PACKAGES • Digitally programmable in 256 delay steps • Monotonic delay-versus-address variation • Two separate outputs: inverting & non-inverting • Precise and stable delays • Input & outputs fully TTL interfaced & buffered • 10 T 2L fan-out capability • Fits standard 40-pin DIP socket • Auto-insertable FUNCTIONAL DESCRIPTION The PDU18F-series device is a 8-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/) depends on the address code (A7-A0) according to the following formula: TDA = TD0 + TINC * A where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation. data delay devices, inc. 3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 N/C OUT/ OUT EN/ GND N/C N/C N/C GND N/C N/C N/C N/C GND N/C EN/ A7 IN N/C GND VCC N/C A0 A1 A2 VCC N/C A3 A4 A5 VCC N/C N/C N/C N/C VCC N/C A6 N/C N/C PDU18F-xx DIP PDU18F-xxC5 Gull-Wing PDU18F-xxM Military DIP PDU18F-xxMC5 Military Gull-Wing PIN DESCRIPTIONS IN Delay Line Input OUT Non-inverted Output OUT/ Inverted Output A0-A7 Address Bits EN/ Output Enable VCC +5 Volts GND Ground DASH NUMBER SPECIFICATIONS Part Number Incremental Delay Per Step (ns) Total Delay Change (ns) PDU18F-.5 .5 ± .3 127.5 ± 6.4 PDU18F-1 1 ± .5 255 ± 12.8 PDU18F-2 2 ± .5 510 ± 25.5 PDU18F-3 3 ± 1.0 765 ± 38.3 PDU18F-4 4 ± 1.0 1,020 ± 51.0 PDU18F-5 5 ± 1.5 1,275 ± 63.8 PDU18F-6 6 ± 1.5 1,530 ± 76.5 PDU18F-8 8 ± 2.0 2,040 ± 102.0 PDU18F-10 10 ± 2.0 2,550 ± 127.5 NOTE: Any dash number between .5 and 10 not shown is also available. SERIES SPECIFICATIONS • Programmed delay tolerance: 5% or 2ns, whichever is greater • Inherent delay (TD0): 13ns typical (OUT) 12ns typical (OUT/) • Setup time and propagation delay: Address to input setup (TAIS): 10ns Disable to output delay (TDISO): 6ns typ. (OUT) • Operating temperature: 0 ° to 70° C • Temperature coefficient: 100PPM/ °C (excludes TD0) • Supply voltage VCC: 5VDC ± 5% • Supply current: ICCH = 65ma ICCL = 128ma • Minimum pulse width: 6% of total delay 1997 Data Delay Devices Doc #97006 DATA DELAY DEVICES, INC. 1 1/30/06 3 Mt. Prospect Ave. Clifton, NJ 07013 |
Similar Part No. - PDU18F-1C5 |
|
Similar Description - PDU18F-1C5 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |