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CY26200SI Datasheet(PDF) 2 Page - Cypress Semiconductor

Part # CY26200SI
Description  T1/E1 Clock Generator
Download  5 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY26200SI Datasheet(HTML) 2 Page - Cypress Semiconductor

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PRELIMINARY
CY26200
Document #: 38-07335 Rev. *A
Page 2 of 5
Pin Summary
Pin Name
Pin Number Pin Description
XIN
1
19.44-MHz Reference Input
AVDD
2
Analog Voltage Supply
FS
3
Frequency Select – see Table 1
AVSS
4
Analog Ground
VDD
5
Voltage Supply
CLK1
6
1.544-MHz/2.048-MHz Clock Output
VSS
7
Ground
XOUT[1]
8
Reference Output
Absolute Maximum Conditions
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
–0.5
7.0
V
TS
Storage Temperature[2]
–65
125
°C
TJ
Junction Temperature
125
°C
Digital Inputs
VSS – 0.3
VDD + 0.3
V
Digital Outputs Referred to VDD
VSS – 0.3
VDD + 0.3
V
Electrostatic Discharge
2000
V
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD/AVDD
Operating Voltage
3.135
3.3
3.465
V
TA
Ambient Temperature (Commercial)
0
70
° C
TA
Ambient Temperature (Industrial)
–40
+85
° C
CLOAD
Max. Load Capacitance
15
pF
fREF
Reference Frequency
19.44
MHz
tPU
Power-up time for all VDD's to reach
minimum specified voltage (power
ramps must be monotonic)
0.05
500
ms
DC Electrical Characteristics (Commercial)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD = 3.3V
12
24
mA
IOL
Output Low Current
VOL = 0.5, VDD = 3.3V
12
24
mA
CIN
Input Capacitance
7pF
IIZ
Input Leakage Current
5
µA
IDD
Supply Current
Sum of Core and Output Current
20
mA
DC Electrical Characteristics (Industrial)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD = 3.3V
11
24
mA
IOL
Output Low Current
VOL = 0.5, VDD = 3.3V
11
24
mA
CIN
Input Capacitance
7pF
IIZ
Input Leakage Current
5
µA
IDD
Supply Current
Sum of Core and Output Current
25
mA
AC Electrical Characteristics (VDD = 3.3V, Commercial)
Parameter[3]
Description
Conditions
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
45
50
55
%
t3
Rising Edge Slew Rate
Output Clock Rise Time, 20% - 80% of VDD
0.8
1.4
V/ns
Notes:
1.
Float XOUT if XIN is externally driven
2.
Rated for 10 years
3.
Not 100% tested


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