Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

3D7444 Datasheet(PDF) 2 Page - Data Delay Devices, Inc.

Part No. 3D7444
Description  MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444)
Download  6 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  DATADELAY [Data Delay Devices, Inc.]
Homepage  http://www.datadelay.com
Logo 

3D7444 Datasheet(HTML) 2 Page - Data Delay Devices, Inc.

   
Zoom Inzoom in Zoom Outzoom out
 2 / 6 page
background image
3D7444
APPLICATION NOTES
line to its normal operation. The device contains
an SO output, which can be used to cascade
multiple devices, as shown in Figure 3.
THEORY OF OPERATION
The quad 4-bit programmable 3D7444 delay line
architecture is comprised of a number of delay
cells connected in series with their respective
outputs multiplexed onto the Delay Out pin (O1-
O4) by the user-selected programming data.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
Each of the four lines can be controlled
independently, via the serial interface.
TABLE 2: BIT SEQUENCE
Bit
Delay
Line
Function
1
4
Output Enable
2
3
Output Enable
3
2
Output Enable
4
1
Output Enable
5
Address Bit 3
6
Address Bit 2
7
Address Bit 1
8
1
Address Bit 0
9
Address Bit 3
10
Address Bit 2
11
Address Bit 1
12
2
Address Bit 0
13
Address Bit 3
14
Address Bit 2
15
Address Bit 1
16
3
Address Bit 0
17
Address Bit 3
18
Address Bit 2
19
Address Bit 1
20
4
Address Bit 0
PROGRAMMED DELAY (ADDRESS)
INTERFACE
Figure 1 illustrates the main functional blocks of
the 3D7444 device. Since the device is a CMOS
design, all unused input pins must be returned to
well defined logic levels (VDD or GND). The
delays are adjusted by first shifting a 20-bit
programming word into the device via the SC and
SI pins, then strobing the AL signal to latch the
values. The bit sequence is shown in Table 2,
and the associated timing diagram is shown in
Figure 2. Each line has associated with it an
enable bit. Setting this bit low will force the
corresponding delay line output to a high
impedance state, while setting it high returns the
DELAY
LINE
20-BIT LATCH
20-BIT SHIFT REGISTER
SO
Figure 1: Functional block diagram
DELAY
LINE
DELAY
LINE
DELAY
LINE
I4
I3
I2
I1
O4
O3
O2
O1
AL
SI
SC
ENABLES
ADDR4
ADDR3
ADDR2
ADDR1
Doc #03006
DATA DELAY DEVICES, INC.
2
12/8/03
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com


Html Pages

1  2  3  4  5  6 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn