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3D7444 Datasheet(PDF) 3 Page - Data Delay Devices, Inc.

Part No. 3D7444
Description  MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444)
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Maker  DATADELAY [Data Delay Devices, Inc.]
Homepage  http://www.datadelay.com
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3D7444 Datasheet(HTML) 3 Page - Data Delay Devices, Inc.

   
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3D7444
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
PROGRAMMED DELAY (ADDRESS)
UPDATE
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7444 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
A delay line is a memory device. It stores
information present at the input for a time equal
to the delay setting before presenting it at the
output with minimal distortion. Each 4-bit delay
line in the 3D7444 can be represented by 15
serially connected delay elements (individually
addressed by the programming data), each
capable of storing data for a time equal to the
device increment (step time). The delay line
memory property, in conjunction with the
operational requirement of “instantaneously”
connecting the delay element addressed by the
programming data to the output, may inject
spurious information onto the output data stream.
The thermal coefficient is reduced to 400
PPM/C, which is equivalent to a variation, over
the 0C-70 C operating range, of
±2% from the
room-temperature delay settings. The power
supply coefficient is reduced, over the 4.75V-
5.25V operating range, to
±1.5% of the delay
settings at the nominal 5VDC power supply
and/or
±2ns, whichever is greater.
In order to ensure that spurious outputs do not
occur, it is essential that the input signal be idle
(held high or low) for a short duration prior to
updating the programmed delay. This duration is
given by the maximum programmable delay.
Satisfying this requirement allows the delay line
to “clear” itself of spurious edges. When the new
address is loaded, the input signal can begin to
switch (and the new delay will be valid) after a
time given by tPDV or tEDV (see section below).
It is essential that the power supply pin be
adequately bypassed and filtered. In addition,
the power bus should be of as low an
impedance construction as possible. Power
planes are preferred.
NEW
VALUES
NEW
BIT 1
NEW
BIT 20
NEW
BIT 2
OLD
BIT 1
OLD
BIT 2
OLD
BIT 20
LATCH
(AL)
CLOCK
(SC)
SERIAL
INPUT
(SI)
SERIAL
OUTPUT
(SO)
DELAY
TIMES
tLW
tCW
tCW
tCSL
tDSC
tDHC
tPCQ
tLDV
tLDX
PREVIOUS VALUES
Figure 2: Serial interface timing diagram
NEW
BIT 1
FROM
WRITING
DEVICE
TO
NEXT
DEVICE
SI
SO
SC
AL
3D7444
3D7444
3D7444
Figure 3: Cascading Multiple Devices
SI
SO
SC
AL
SI
SO
SC
AL
Doc #03006
DATA DELAY DEVICES, INC.
3
12/8/03
3 Mt. Prospect Ave. Clifton, NJ 07013


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