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3D7418 Datasheet(PDF) 4 Page - Data Delay Devices, Inc.

Part No. 3D7418
Description  MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE)
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Maker  DATADELAY [Data Delay Devices, Inc.]
Homepage  http://www.datadelay.com
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3D7418 Datasheet(HTML) 4 Page - Data Delay Devices, Inc.

   
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3D7418
APPLICATION NOTES (CONT’D)
pin (SI) of the succeeding device, as illustrated in
Figure 5. The total number of serial data bits in
a cascade configuration must be eight times the
number of units, and each group of eight bits
must be transmitted in MSB-to-LSB order.
To initiate a serial read, enable (AE) is driven
high. After a time tEQV , bit 7 (MSB) is valid at the
serial output port pin (SO). On the first rising
edge of the serial clock (SC), bit 7 is loaded with
the value present at the serial data input pin (SI),
while bit 6 is presented at the serial output pin
(SO). To retrieve the remaining bits seven more
rising edges must be generated on the serial
clock line. The read operation is destructive.
Therefore, if it is desired that the original delay
setting remain unchanged, the read data must be
written back to the device(s) before the enable
(AE) pin is brought low.
Pin 3, if unused, must be allowed to float if the
device is configured in the serial programming
mode.
PROGRAMMABLE
DELAY LINE
LATCH
8-BIT INPUT
REGISTER
MD
SC
SI
AE
IN
SO
OUT
P0 P1 P2 P3 P4 P5 P6 P7
MODE SELECT
SHIFT CLOCK
SERIAL INPUT
ADDRESS ENABLE
SIGNAL IN
SIGNAL OUT
SERIAL OUTPUT
PARALLEL INPUTS
Figure1: Functional block diagram
PREVIOUS VALUE
PREVIOUS VALUE
NEW VALUE
NEW VALUE
tPDX
tPDV
PARALLEL
INPUTS
P0-P7
DELAY
TIME
Figure 2: Non-latched parallel mode (MD=1, AE=1)
PREVIOUS VALUE
NEW VALUE
NEW VALUE
tEDX
tEDV
PARALLEL
INPUTS
P0-P7
DELAY
TIME
tDSE
tDHE
tEW
ENABLE
(AE)
Figure 3: Latched parallel mode (MD=1)
Doc #02005
DATA DELAY DEVICES, INC.
4
6/17/02
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com


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