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PC8374L0VLA Datasheet(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC8374L0VLA
Description  SensorPathTM SuperI/O with Glue Functions
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC8374L0VLA Datasheet(HTML) 7 Page - National Semiconductor (TI)

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Table of Contents (Continued)
Revision 1.1
7
www.national.com
3.2.1
The Index-Data Register Pair ...................................................................................... 38
3.2.2
Banked Logical Device Registers Structure ................................................................ 38
3.2.3
Standard Configuration Register Definitions ............................................................... 39
3.2.4
Standard Configuration Registers ............................................................................... 42
3.2.5
Default Configuration Setup ........................................................................................ 43
3.2.6
Memory Space Mapping .............................................................................................. 44
3.3
MODULE CONTROL ................................................................................................................. 48
3.3.1
Module Enable/Disable ................................................................................................ 48
3.3.2
Floating Module Output ............................................................................................... 48
3.4
INTERNAL ADDRESS DECODING .......................................................................................... 49
3.5
PROTECTION ........................................................................................................................... 50
3.5.1
Multiplexed Pins Configuration Lock ........................................................................... 50
3.5.2
GPIO Ports Configuration Lock ................................................................................... 50
3.5.3
Fast Disable Configuration Lock .................................................................................. 50
3.5.4
Clock Control Lock ...................................................................................................... 50
3.5.5
GPIO Port Lock ........................................................................................................... 50
3.5.6
Health Management Configuration Lock ..................................................................... 50
3.5.7
SWC Configuration Lock ............................................................................................. 50
3.6
REGISTER TYPE ABBREVIATIONS ........................................................................................ 51
3.7
PC8374L CONFIGURATION REGISTERS ............................................................................... 52
3.7.1
Memory Mapping Control Register (MEMMAP) .......................................................... 52
3.7.2
Memory Base Address Register 1 (MEMADR1) ......................................................... 53
3.7.3
Memory Base Address Register 2 (MEMADR2) ......................................................... 53
3.7.4
SuperI/O ID Register (SID) .......................................................................................... 53
3.7.5
SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 54
3.7.6
SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 55
3.7.7
SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 56
3.7.8
SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 57
3.7.9
SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 57
3.7.10
SuperI/O Revision ID Register (SRID) ........................................................................ 58
3.7.11
Clock Generator Control Register (CLOCKCF) ........................................................... 59
3.7.12
Health Management SMBus Configuration (HMSMBCF) Register ............................. 59
3.8
FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 60
3.8.1
General Description ..................................................................................................... 60
3.8.2
Logical Device 0 (FDC) Configuration ......................................................................... 60
3.8.3
FDC Configuration Register ........................................................................................ 61
3.8.4
Drive ID Register ......................................................................................................... 62
3.9
PARALLEL PORT (PP) CONFIGURATION .............................................................................. 63
3.9.1
General Description ..................................................................................................... 63
3.9.2
Logical Device 1 (PP) Configuration ............................................................................ 63
3.9.3
Parallel Port Standard Configuration Register ............................................................. 64
3.9.4
Parallel Port Modified Configuration Register .............................................................. 65
3.10
SERIAL PORT 2 WITH INFRARED CONFIGURATION ........................................................... 66
3.10.1
General Description ..................................................................................................... 66
3.10.2
Logical Device 2 (SP2) Configuration .......................................................................... 66
Winbond Electronics Corp. Advanced PC Product Center


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