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MAX1261 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. MAX1261
Description  250ksps, 3V, 8-/4-Channel, 12-Bit ADCs with 2.5V Reference and Parallel Interface
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Maker  MAXIM [Maxim Integrated Products]
Homepage  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1261 Datasheet(HTML) 4 Page - Maxim Integrated Products

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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle); TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Shutdown mode
Standby mode
Operating mode,
fSAMPLE = 250ksps
µA
210
0.9
1.2
mA
2.3
2.6
V
2.7
3.6
VDD
Analog Supply Voltage
150
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty
cycle); TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.)
VLOGIC Current
ILOGIC
CL = 20pF
210
µA
Power-Supply Rejection
PSR
VDD = 3V ±10%, full-scale input
±0.4
±0.9
mV
fSAMPLE = 250ksps
Not converting
V
1.8
VDD +
0.3
VLOGIC
Digital Supply Voltage
WR to CLK Fall Setup Time
tCWS
40
ns
ns
CLK Pulse Width High
ns
CLK Period
tCH
40
tCP
208
CLK Pulse Width Low
tCL
40
ns
Data Valid to WR Rise Time
tDS
40
ns
WR Rise to Data Valid Hold Time
tDH
0
ns
CLK Fall to WR Hold Time
tCWH
40
ns
CS to CLK or WR
Setup Time
tCSWS
60
ns
CLK or WR to CS
Hold Time
tCSWH
0
ns
CS Pulse Width
tCS
100
ns
WR Pulse Width
tWR
60
ns
tTC
20
100
ns
(Note 8)
CLOAD = 20pF (Figure 1)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
CS Rise to Output Disable
POWER REQUIREMENTS
Internal reference
Internal reference
External reference
External reference
1.9
2.3
0.5
0.8
IDD
Positive Supply Current


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