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CY7C09569V
CY7C09579V
Document #: 38-06054 Rev. *B
Page 10 of 30
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)
[10, 11, 12, 13]
Read Cycle for Pipelined Operation (FT/PIPE = VIH)
[10, 11, 12, 13]
Notes:
10. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
11. ADS = VIL, CNTEN = VIL and CNTRST = VIH.
12. The output is disabled (high-impedance state) by CE=VIH following the next rising edge of the clock.
13. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
tCH1
tCL1
tCYC1
tSC
tHC
tDC
tOHZ
tOE
tSC
tHC
tSW
tHW
tSA
tHA
tCD1
tCKHZ
tDC
tOLZ
tCKLZ
An
An+1
An+2
An+3
Qn
Qn+1
Qn+2
CLK
CE
R/W
ADDRESS
DATAOUT
OE
tSB
tHB
B0-3
tCH2
tCL2
tCYC2
tSC
tHC
tSW
tHW
tSA
tHA
An
An+1
CLK
CE
R/W
ADDRESS
DATAOUT
OE
An+2
An+3
tSC
tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
Qn
Qn+1
Qn+2
1 Latency
tSB
tHB
B0-3
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