3.3V 16K/32K x 36
FLEx36™ Synchronous Dual-Port Static RAM
CY7C09569V
CY7C09579V
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06054 Rev. *B
Revised April 18, 2005
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 16K x 36 organization (CY7C09569V)
— 32K x 36 organization (CY7C09579V)
• 0.25-micron CMOS for optimum speed/power
•Three modes
— Flow-Through
— Pipelined
—Burst
• Bus-Matching Capabilities on Right Port
(x36 to x18 or x9)
• Byte-Select Capabilities on Left Port
• 100-MHz Pipelined Operation
• High-speed clock to data access 5/6/8 ns
• 3.3V Low operating power
— Active = 250 mA (typical)
— Standby = 10
μA (typical)
• Fully synchronous interface for ease of use
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Counter Address Read Back via I/O lines
• Single Chip Enable
• Automatic power-down
• Commercial and Industrial Temperature Ranges
• Compact package
— 144-Pin TQFP (20 x 20 x 1.4 mm)
— 144-Pin Pb-Free TQFP (20 x 20 x 1.4 mm)
— 172-Ball BGA (1.0-mm pitch) (15 x 15 x 0.51 mm)
Note:
1. A0–A13 for 16K; A0–A14 for 32K devices.
Logic Block Diagram
R/WL
B0–B3
OEL
FT/PipeL
I/O18L–I/O26L
A0–A13/14L
CLKL
ADSL
CNTENL
CNTRSTL
A0–A13/14R
CLKR
ADSR
CNTENR
CNTRSTR
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
9
[1]
[1]
14/15
14/15
I/O27L–I/O35L
9
I/O0L–I/O8L
9
I/O9L–I/O17L
9
CEL
I/O
Control
Left
Port
Control
Logic
R/WR
OER
FT/PipeR
9
9
I/OR
9
9
CER
I/O
Control
Right
Port
Control
Logic
Bus
Match
9/18/36
BM
SIZE
BE
CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K x 36
FLEx36™ Synchronous Dual-Port Static RAM
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