IS27HC010-70T datasheet(7/11 Pages) ISSI

Part #	IS27HC010-70T

Description	131,072 x 8 HIGH-SPEED CMOS EPROM

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

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7 / 11 page

ISSI®

IS27HC010

Integrated Silicon Solution, Inc.

7

EP009-1F

07/18/97

SWITCHING CHARACTERISTICS(1,3,4) (Over Operating Range)

JEDEC

Std.

-30

-45

-70

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Min.

Max.

Unit

tAVQA

tACC

Address to

CE = OE = VIL

—30

—

45

—70

ns

Output Delay

CL = CL1

tELQV

tCE

Chip Enable to

OE = VIL

—30

—

45

—70

ns

Output Delay

CL = CL1

tGLQV

tOE

Output Enable to

CE = VIL

—10

—

20

—35

ns

Output Delay

CL = CL1

tEHOZ,

tDF(2)

Chip Enable HIGH or

CL = CL2

010

0

20

035

ns

tGHQZ

Output Enable HIGH,

whichever comes first,

to Output Float

tAVOX

tOH

Output Hold from

0

—

0

—

0

—

ns

Address,

CE or OE

whichever occured first

Notes:

1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

2. This parameter is only sampled, not 100% tested.

3. Caution: The IS27HC010 must not be removed from (or inserted into) a socket or board when VPP or VCC applied.

4. Output Load: 1 TTL gate and C = CL.

Input Rise and Fall times: 2 ns.

Input Pulse Levels: 0 to 3V.

Timing Measurement Reference Level: 1.5V for inputs and outputs.

ADDRESS

CE

OE

OUTPUT

ADDRESS VALID

VALID OUTPUT

1.5V

tDF(2)

tOH

Hi-Z

tOE

tACC(1)

tCE

3V

0V

1.5V

SWITCHING WAVEFORMS

Notes:

1.

OE may be delayed up to tACC – tOE after the falling edge of CE without impact on tACC.

2. tDF is specified from

OE or CE, whichever occurs first.

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IS27HC010-70T Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc

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