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HMC1126ACEZ Datasheet(PDF) 6 Page - Analog Devices

Part # HMC1126ACEZ
Description  GaAs, pHEMT, Low Noise Amplifier, 400 MHz to 52 GHz
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

HMC1126ACEZ Datasheet(HTML) 6 Page - Analog Devices

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HMC1126ACEZ
Data Sheet
Rev. 0 | Page 6 of 21
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
1
3
4
5
6
18
17
16
15
14
13
GND
GND
RFIN
GND
GND
GND
GND
GND
GND
RFOUT
GND
GND
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD
TO A GROUND PLANE WITH LOW THERMAL
AND ELECTRICAL IMPEDENCE.
HMC1126ACEZ
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 3, 5, 6, 7, 9, 11 to 15,
17, 18, 19, 21 to 24
GND
Ground. All the ground pins must be connected to a low impedance ground plane. See Figure 7 for
the interface schematic.
4
RFIN
RF Input. RFIN is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic.
8
VGG1
Gate Control 1 for the Amplifier. Adjust VGG1 to achieve IDQ = 85 mA. See Figure 6 for the interface
schematic.
10
VGG2
Gate Control 2 for the Amplifier. For nominal operation, apply 1 V to VGG2. See Figure 5 for the
interface schematic.
16
RFOUT
RF Output. RFOUT is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic.
20
VDD
Drain Supply Voltage with Integrated RF Choke. Connect the dc bias to VDD to provide IDQ. See Figure 4
for the interface schematic.
EPAD
Exposed Pad. Connect the exposed pad to a ground plane with low thermal and electrical
impedance.
INTERFACE SCHEMATICS
RFIN
Figure 3. RFIN Interface Schematic
RFOUT
VDD
Figure 4. VDD and RFOUT Interface Schematic
VGG2
Figure 5. VGG2 Interface Schematic
VGG1
Figure 6. VGG1 Interface Schematic
GND
Figure 7. GND Interface Schematic


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