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HT46R14 Datasheet(PDF) 5 Page - Holtek Semiconductor Inc |
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HT46R14 Datasheet(HTML) 5 Page - Holtek Semiconductor Inc |
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5 / 47 page  A.C. Characteristics Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS System Clock ¾ 2.2V~5.5V 400 ¾ 4000 kHz ¾ 3.3V~5.5V 400 ¾ 8000 kHz fTIMER Timer I/P Frequency (TMR0/TMR1) ¾ 2.2V~5.5V 0 ¾ 4000 kHz ¾ 3.3V~5.5V 0 ¾ 8000 kHz tWDTOSC Watchdog Oscillator Period 3V ¾ 45 90 180 ms 5V ¾ 32 65 130 ms tRES External Reset Low Pulse Width ¾¾ 1 ¾¾ ms tSST System Start-up Timer Period ¾ Power-up or Wake-up from HALT ¾ 1024 ¾ *tSYS tINT Interrupt Pulse Width ¾¾ 1 ¾¾ ms tAD A/D Clock Period ¾¾ 1 ¾¾ ms tADC A/D Conversion Time ¾¾ ¾ 76 ¾ tAD tADCS A/D Sampling Time ¾¾ ¾ 32 ¾ tAD tCOMP Comparator Response Time ¾¾ ¾ ¾ 3 ms Note: *tSYS=1/fSYS HT46R14 Rev. 1.00 5 November 1, 2005 Functional Description Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de- coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in program PROM are exe- cuted and its contents specify full range of program memory. After accessing a program memory word to fetch an in- struction code, the contents of the program counter are in- cremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call, initial re- set, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k O S C 2 ( R C o n l y ) P C Execution Flow |
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