DG894

Vishay Siliconix

Document Number: 70072

S-52433—Rev. D, 06-Sep-99

www.siliconix.com

S FaxBack 408-970-5600

5-9

SDA

SCL

STA

STO

SDA

SCL

Start Condition

Stop Condition

FIGURE 8. START and STOP Conditions

1

2

7

8

9

1

2

3-8

9

STA

Start Condition

STO

Stop

Condition

ACK

ACK

MSB

SDA

SCL

acknowledgement

signal from receiver

acknowledgement

signal from receiver

clock line held low while interrupts are serviced

byte complete, interrupt within receiver

4 k

W pull-up resistors to +5 V; 200 pF capacitor to

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

–

100

kHz

Bus Free Before Start

4.7

–

Start Condition Set-up Time

4.7

–

Start Condition Hold Time

4

–

SCL and SDA Low Period

4.7

–

SCL and SDA High Period

4

–

ms

SCL and SDA Rise Time

–

1.0

SCL and SDA Fall Time

–

0.3

Data Set-Up Time (WRITE)

0.25

–

Data Hold Time (WRITE)

0*

–

*A transmitter must internally provide at lease a hold time to bridge the

undefined region (max 300 ns) of the falling edge of the SCL.

four allocated addresses, two of which are user programmable

through the SEL pin. Additional addresses may be obtained by

a metal mask option for users requiring more than two DG894s

further information.

After the correct address has been sent, only one data byte is

needed to define the switch configuration. Subsequent data

put onto the bus will update the switches until a STOP

condition (or another START condition) signals that the device

is no longer being addressed. The switches will then remain in

their last configuration as long as power is maintained to the

chip.

Power on Reset

A power on reset function is provided on the DG894 to turn all

the CMOS control mode, the switches are selected according

to the state of the control inputs.