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CYNSE70032 Datasheet(PDF) 22 Page - Cypress Semiconductor

Part # CYNSE70032
Description  Network Search Engine
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE70032 Datasheet(HTML) 22 Page - Cypress Semiconductor

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CYNSE70032
Document #: 38-02042 Rev. *E
Page 22 of 126
The following is the Write operation sequence, and Table 12-7 shows the Write address format for the data array, the mask array,
or the single-Write SRAM. Table 12-8 shows the Write address format for the internal registers.
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the address supplied
on the DQ bus. The host ASIC also supplies the GMR Index to mask the write to the data or mask array location on CMD[5:3].
For SRAM Writes, the host ASIC must supply SADR[21:19] on CMD[8:6].
• Cycle 1B: The host ASIC continues to apply the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the address
supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask array
locations in CMD[5:3]. The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the devices
when DQ[25:21] = 11111.
• Cycle 2: The host ASIC drives the DQ[67:0] with the data to be written to the data array, the mask array, or the register location
of the selected device.
• Cycle 3: Idle cycle.
At the termination of cycle 3, another operation can begin. Note. The latency of the SRAM Write will be different than the one
described above (see Subsection 15.2, “SRAM PIO Access” on page 99).
Figure 12-4 shows the timing diagram of a burst Write operation of the data or mask array.
Table 12-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write)
DQ
[67:30]
DQ
[29]
DQ
[28:26]
DQ
[25:21]
DQ
[20:19]
DQ
[18:14]
DQ[13:0]
Reserved 0: Direct
1: Indirect
SSR (applicable if
DQ[29] is indirect)
ID
00:
Data
Array
Reserved If DQ[29] is 0, this field carries the address of the data
array location. If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of the data
array location: {SSR[13:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}.[6]
Reserved 0: Direct
1: Indirect
SSR (applicable if
DQ[29] is indirect)
ID
01:
Mask
Array
Reserved If DQ[29] is 0, this field carries the address of the
mask array location. If DQ[29] is 1, the SSR specified
on DQ[28:26] is used to generate the address of the
mask array location: {SSR[13:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}.[6]
Reserved 0: Direct
1: Indirect
SSR (applicable if
DQ[29] is indirect)
ID
10:
External
SRAM
Reserved If DQ[29] is 0, this field carries the address of the
SRAM location. If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of the
SRAM location: {SSR[13:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}.[6]
Table 12-8. Write Address Format for Internal Registers
DQ[67:26]
DQ[25:21]
DQ[20:19]
DQ[18:6]
DQ[5:0]
Reserved
ID
11: Register
Reserved
Register address
cycle 2
cycle 3
Write
Address
Data
CMDV
CMD[1:0]
DQ
X
cycle 1
cycle 0
cycle 4
CMD[8:2]
B
PHS_L
A
CLK2X
Figure 12-3. Single Write Cycle Timing


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