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CYNSE70032 Datasheet(PDF) 92 Page - Cypress Semiconductor

Part # CYNSE70032
Description  Network Search Engine
Download  126 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE70032 Datasheet(HTML) 92 Page - Cypress Semiconductor

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CYNSE70032
Document #: 38-02042 Rev. *E
Page 92 of 126
13.11
LRAM and LDEV Description
When search engines are cascaded using multiple CYNSE70032 devices, the SADR, CE_L, and WE_L (three-state signals) are
all tied together. To eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For
non-Search or non-Learn cycles (see Subsection 13.12, “Learn Command” on page 92) or Search cycles with a global miss, the
SADR, CE_L, and WE_L signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of
cascaded search engines have this bit set. Failure to do so will cause contention on SADR, CE_L, and WE_L, and can potentially
cause damage to the device(s).
Similarly, when search engines using multiple CYNSE70032 devices are cascaded, SSF and SSV (also three-state signals) are
tied together. To eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For nonSearch
cycles or Search cycles with a global miss, the SSF and SSV signals are driven by the device with the LDEV bit set. It is important
that only one device in a bank of cascaded search engines have this bit set. Failure to do so will cause contention on SSV and
SSF and can potentially cause damage to the device(s).
13.12
Learn Command
Bit[0] of each 68-bit data location specifies whether an entry in the database is occupied. If all the entries in a device are occupied,
the device asserts FULO signal to inform the downstream devices that it is full. The result of this communication between
depth-cascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines
the fullness of the depth-cascaded table.
The device contains sixteen pairs of internal, 68-bit-wide comparand registers that store the comparands as the device executes
searches. On a miss by the Search (signalled to ASIC through the SSV and SSF signals [SSV = 1, SSF = 0]), the host ASIC can
apply the Learn command to Learn the entry from a comparand register to the next-free location (see Subsection 9.3, “NFA
Register” on page 16). The NFA updates to the next-free location following each Write or Learn command.
In a depth-cascaded table, only a single device will Learn the entry through the application of a Learn instruction. The determi-
nation of the Learn device is based on the FULI and FULO signalling between the devices. The first non-full device learns the
entry by storing the contents of the specified comparand registers to the location(s) pointed to by NFA.
In a ×68-configured table the Learn command writes a single 68-bit location. In a ×136-configured table the Learn command
writes the next even and odd 68-bit locations. In 136-bit mode, bit[0] of the even and odd 68-bit locations is 0, indicating that they
are cascaded empty, or 1, which indicates that they are occupied.
The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no
more entries can be learned. The CYNSE70032 device updates the signal to a data array after each Write or Learn command.
Also using the NFA register as part of the SRAM address, the Learn command generates a Write cycle to the external SRAM
(see Section 15.0, “SRAM Addressing” on page 98).
The Learn command is supported on a single block containing up to eight devices if the table is configured as either a ×68 or a
×136. The Learn command is not supported for ×272-configured tables.
Learn is a pipelined operation and lasts for two CLK cycles where TLSZ = 00, as shown in Figure 13-69, and TLSZ = 01 as shown
in Figure 13-70 and Figure 13-71. Figure 13-70 and Figure 13-71 assume that the device performing the Learn operation is not
the last device in the table and has its LRAM bit set to 0. Note. The OE_L for the device with the LRAM bit set goes high for two
cycles for each Learn (one during the SRAM Write cycle, and one during the cycle before it). The latency of the SRAM Write cycle
from the second cycle of the instruction is shown in Table 13-25.


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