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CYNSE70032 Datasheet(PDF) 76 Page - Cypress Semiconductor

Part # CYNSE70032
Description  Network Search Engine
Download  126 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE70032 Datasheet(HTML) 76 Page - Cypress Semiconductor

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CYNSE70032
Document #: 38-02042 Rev. *E
Page 76 of 126
The logical 272-bit Search operation is shown in Figure 13-52. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and the local mask bits. The GMR is
the 272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C in each of
the eight devices. The 272-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to
each entry in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as
part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 98). Note. The matching address is always
going to be a location 0 in a four-entry page for 272-bit Search (two LSBs of the matching index will be 00).
The Search command is a pipelined operation and executes a Search at one-fourth the rate of the frequency of CLK2X for 272-bit
searches in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search
command (measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 13-20.
Search latency from command to SRAM access cycle is 5 for only a single device in the table and TLSZ = 01. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 13-21.
13.9
272-bit Search on Tables Configured as ×272 using up to 31 CYNSE70032 Devices
The hardware diagram of the search subsystem of 31 devices is shown in Figure 13-53. Each of the four blocks in the diagram
represents a block of eight CYNSE70032 devices, except the last which has seven devices. The diagram for a block of eight
devices is shown in Figure 13-54. The following are the parameters programmed into the 31 devices.
• First thirty devices (devices 0–29): CFG = 10101010, TLSZ = 10, HLAT = 000, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 10101010, TLSZ = 10, HLAT = 000, LRAM = 1, and LDEV = 1.
Table 13-20. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
Max Table Size
Latency in CLK Cycles
1 (TLSZ = 00)
4K × 272 bits
4
1–8 (TLSZ = 01)
32K × 272 bits
5
1–31 (TLSZ = 10)
124K × 272 bits
6
Table 13-21. Shift of SSF and SSV from SADR
HLAT
Number of CLK Cycles
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
CFG = 10101010
271
0
Location
0
4
8
12
131068
(272-bit configuration)
address
K
GMR
271
0
L
A
B
01
C
D
23
(First matching entry)
Must be same in each of the eight
devices
Figure 13-52. x272 Table with Eight Devices


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