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CY241V08A-41 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY241V08A-41
Description  MPEG Clock Generator with VCXO
Download  6 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY241V08A-41 Datasheet(HTML) 3 Page - Cypress Semiconductor

   
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CY241V08A-41
Document #: 38-07655 Rev. *A
Page 3 of 6
Absolute Maximum Conditions
Supply Voltage (VDD) ........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-condensing).....–55
°C to +125°C
Junction Temperature ................................ –40
°C to +125°C
Data Retention @ Tj = 125
°C................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883................. > 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Pullable Crystal Specifications[1]
Parameter
Description
Comments
Min. Typ. Max.
Unit
FNOM
Nominal crystal frequency
Parallel resonance, fundamental mode, AT
cut
–27
MHz
CLNOM
Nominal load capacitance
14
pF
R1
Equivalent series resistance (ESR)
Fundamental mode
25
R3/R1
Ratio of third overtone mode ESR to
fundamental mode ESR
Ratio used because typical R1 values are
much less than the maximum spec
3–
DL
Crystal drive level
No external series resistor assumed
150
µW
F3SEPHI
Third overtone separation from 3*FNOM High side
300
ppm
F3SEPLO
Third overtone separation from 3*FNOM Low side
–150
ppm
C0
Crystal shunt capacitance
7
pF
C0/C1
Ratio of shunt to motional capacitance
180
250
C1
Crystal motional capacitance
14.4
18
21.6
fF
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
3.135
3.3
3.465
V
TA
Ambient Temperature
0
70
°C
CLOAD
Max. Load Capacitance
15
pF
tPU
Power-up time for all VDD pins to reach minimum specified
voltage (power ramps must be monotonic)
0.05
500
ms
DC Electrical Specifications
Parameter
Name
Description
Min.
Typ.
Max.
Unit
IOH
Output HIGH Current
VOH = VDD – 0.5V, VDD = 3.3V
12
24
mA
IOL
Output LOW Current
VOL = 0.5V, VDD = 3.3V
12
24
mA
CIN
Input Capacitance
Except XIN, XOUT pins
7
pF
VVCXO
VCXO Input Range
0
VDD
V
f∆XO[2]
VCXO Pullability Range
Low Side
–115
ppm
High Side
115
ppm
IVDD
Supply Current
40
mA
AC Electrical Specifications (VDD = 3.3V) [3]
Parameter[3]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of VDD
45
50
55
%
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20%
to 80% of VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15 pF. See Figure 2.
0.8
1.4
V/ns
Notes:
1.
Crystals that meet this specification includes: Ecliptek ECX-5808-27.000M
2.
–115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less
board capacitance.
3.
Not 100% tested.


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