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CY7C1327G Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C1327G
Description  4-Mbit (256K x 18) Pipelined Sync SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1327G Datasheet(HTML) 10 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1327G
Document #: 38-05519 Rev. *A
Page 10 of 18
Switching Characteristics Over the Operating Range[14, 15]
Parameter
Description
250 MHz
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Unit
Min. Max Min.
Max
Min.
Max
Min.
Max
Min. Max Min. Max
tPOWER
VDD(Typical) to the first
[10]
1
1
1
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
4.4
5.0
6.0
7.5
10
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.5
3.0
3.5
ns
tCL
Clock LOW
1.7
2.0
2.0
2.5
3.0
3.5
ns
Output Times
tCO
Data Output Valid After CLK
Rise
2.6
2.6
2.8
3.5
4.0
4.5
ns
tDOH
Data Output Hold After CLK
Rise
1.0
1.0
1.0
1.5
1.5
1.5
ns
tCLZ
Clock to Low-Z[11, 12, 13]
0
0
0
0
0
0
ns
tCHZ
Clock to High-Z[11, 12, 13]
2.6
2.6
2.8
3.5
4.0
4.5
ns
tOEV
OE LOW to Output Valid
2.6
2.6
2.8
3.5
4.5
4.5
ns
tOELZ
OE LOW to Output Low-Z
[11,
12, 13]
0
0
0
0
0
0
ns
tOEHZ
OE HIGH to Output High-Z
[11,
12, 13]
2.6
2.6
2.8
3.5
4.0
4.5
ns
Set-up Times
tAS
Address Set-up Before CLK
Rise
1.2
1.2
1.2
1.5
1.5
1.5
ns
tADS
ADSC, ADSP Set-up Before
CLK Rise
1.2
1.2
1.2
1.5
1.5
1.5
ns
tADVS
ADV Set-up Before CLK Rise
1.2
1.2
1.2
1.5
1.5
1.5
ns
tWES
GW, BWE, BWX Set-up Before
CLK Rise
1.2
1.2
1.2
1.5
1.5
1.5
ns
tDS
Data Input Set-up Before CLK
Rise
1.2
1.2
1.2
1.5
1.5
1.5
ns
tCES
Chip Enable Set-Up Before
CLK Rise
1.2
1.2
1.2
1.5
1.5
1.5
ns
Hold Times
tAH
Address Hold After CLK Rise
0.3
0.5
0.5
0.5
0.5
0.5
ns
tADH
ADSP , ADSC Hold After CLK
Rise
0.3
0.5
0.5
0.5
0.5
0.5
ns
tADVH
ADV Hold After CLK Rise
0.3
0.5
0.5
0.5
0.5
0.5
ns
tWEH
GW,BWE, BWX Hold After
CLK Rise
0.3
0.5
0.5
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK
Rise
0.3
0.5
0.5
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK
Rise
0.3
0.5
0.5
0.5
0.5
0.5
ns
Shaded areas contain advance information.
Notes:
10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets.
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.


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