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AT52BC1661A Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT52BC1661A Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 34 page  5 AT52BC1661A(T) [Preliminary] 3455A–STKD–11/04 16-Mbit Flash Description The 16-Mbit Flash is organized as 1,048,576 words of 16 bits each. The x16 data appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations. The device has CE and OE control signals to avoid any bus contention. This device can be read or reprogrammed using a single power supply, making it ideally suited for in-system programming. The device powers on in the read mode. Command sequences are used to place the device in other operation modes such as program and erase. The device has the capability to protect the data in any sector (see “Sector Lockdown” section). To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the memory. The end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the toggle bit. The VPP pin provides data protection. When the VPP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase opera- tions can be performed. A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode (Single Pulse Word Program) is exited by powering down the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to V CC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not work while in this mode; if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code. Device Operation READ: The Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the out- puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual- line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or standby mode, depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the “Command Definition in Hex” table on page 13 (I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. |
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