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ML9261A Datasheet(PDF) 4 Page - OKI electronic componets

Part No. ML9261A
Description  60-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver
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Manufacturer  OKI [OKI electronic componets]
Direct Link  http://www.oki.com
Logo OKI - OKI electronic componets

ML9261A Datasheet(HTML) 4 Page - OKI electronic componets

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FEDL9261A-01
OKI Semiconductor
ML9261A
4/16
PIN DESCRIPTION
Symbol
Type
Description
CLK
l
Shift register clock input pin.
Shift register reads data from DIN while the CLK pin is low and the data in the shift
register is shifted from one stage to the next stage at the rising edge of the clock.
DIN
I
Serial data input pin of the shift register.
Display data (positive logic) is input in the DIN pin in synchronization with clock.
DOUT
O
Serial data output pin of the shift register.
Data is output from the DOUT pin in synchronization with the CLK signal.
LS
I
Latch strobe input pin.
The contents of the parallel outputs (PO1 to PO60) of the shift register are read at the
rising edge of LS (edge-triggered). When the CLK rises while LS is high, the parallel
outputs (PO1 to PO60) and latch outputs (O1 to O60) go low.
CL
I
Clear input pin with a built-in pull-down resistor.
The
CL pin is normally set high.
If the
CL pin is high and the CHG pin is low, the driver outputs (HVO1 to HVO60) are in
phase with the corresponding register outputs (O1 to O60).
If the
CL pin is high and the CHG pin is high, the driver outputs (HVO1 to HVO60) are
high irrespective of the states of the register outputs.
If the
CL pin is set low, the driver outputs are driven low irrespective of the states of the
CHG pin and register outputs.
This allows display blanking to be set.
CHG
I
Input for testing (with a pull-down resistor).
The
CL pin is normally set low.
If the CHG pin is low and the
CL pin is high, the driver outputs (HVO1 to HVO60) are in
phase with the corresponding register outputs (O1 to O60).
If the CHG pin is low and the
CL pin is low, the driver outputs (HVO1 to HVO60) are low
irrespective of the states of the register outputs.
If the CHG pin is set high, the driver outputs are driven high irrespective of the states of
the register outputs.
This provides the easy testing of all lights after final assembly.
VHO1-60
O
High voltage driver outputs for driving a VFD tube.
If the
CL pin is high and the CHG pin is low, the driver outputs are in phase with the
corresponding register outputs (O1 to O60).
The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors.
VDISP
Power supply pin for VFD tube driver circuits
VDD
Power supply pin for logic
D-GND
GND pin for VFD tube driver circuits.
Since the D-GND pin is not connected internally to the L-GND pin, connect these pins
outside of the IC.
L-GND
GND pin for the logic circuits.
Since the L-GND pin is not connected internally to the D-GND pin, connect thiese pins
outside of the IC.


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