FEDL9090A-01

1Semiconductor

ML9090A-01, -02

29/41

Display Screen and Memory Address Allocation

The ML9090A-01/02 contains display data RAM (80 bits by 18 bits) of a bitmap type.

The allocation of memory addresses varies according to the selected word length (6 bits or 8 bits) as shown in

Figure 2: 0 to 9 for selection of 8 bits per word or 0 to 13 for selection of 6 bits per word.

The X address 13 in the 6-bits/word mode has two display memory bits. The two bits (D5 and D4) starting from bit

D5 of the display data register are written in memory and the other bits (D3 to D0) are ignored.

Address Allocation in the 8-bits/word mode

Address Allocation in the 6-bits/word mode

0

1

2

9

0

1

17

(X address)

(D7)

(D0)

(8 bits)

0

1

2

13

0

1

17

(X address)

(D5)

(D0)

(6 bits)

(D5)

(D4)

(2 bits)

Figure 2 Display Memory Addresses

In the 8-bits/word mode, data to be displayed is written in display memory with the D7 data of the display data

register at address (Xn, Yn) and the D0 data at address (Xn + 7, Yn). Similarly, In the 6-bits/word mode, data to be

displayed is written in display memory with the D5 data of the display data register at address (Xn, Yn) and the D0

data at address (Xn + 5, Yn). See Figure 3.

Data “1” in display memory represents turning on the corresponding display segment and data “0” in display

memory represents turning off the corresponding display segment.

0

0

0

0

11

1

11

X address

Y0

Y1

Y17

Common

output

(COM1)

(COM2)

(COM18)

RAM for 80 dots by 18 dots display

(D7)

(D5)

(D0) For 8 bits per word

(D0) For 6 bits per word

Figure 3 Display Screen Bit Allocation and Memory Addresses