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MSM5424331 Datasheet(PDF) 6 Page - OKI electronic componets

Part No. MSM5424331
Description  222,720-Word × 24-Bit Field Memory
Download  34 Pages
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Maker  OKI [OKI electronic componets]
Homepage  http://www.oki.com
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MSM5424331 Datasheet(HTML) 6 Page - OKI electronic componets

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FEDS5424331-01
1Semiconductor
MSM5424331
6/34
PIN FUNCTION
Read Related
D/F
This signal switches between the FIFO mode and the Block Access mode. The FIFO mode is selected when this
signal is low “L” and the Block Access mode is selected when this signal is high “H”.
RCLK: Read Clock
RCLK is the read control clock input in the FIFO mode. Synchronized with RCLK’s rising edge, serial read access
from read ports is executed when
RE is low.
The internal counter for the serial read address is incremented automatically on the rising edge of RCLK. In a read
address set cycle, all the read address bits which were input from RXAD pin are stored into internal address
registers synchronized with RCLK. In this address set cycle, RADE/RX must be held high and RR must be held
low.
In the read address reset cycle, various read address reset modes can be set synchronously with RCLK. These reset
cycles work to replace complicated serial address control which requires many RCLK clocks with a simple reset
cycle control requiring only a single RCLK cycle. It greatly facilitates memory access.
In the Block Access mode, the RCLK signal is ignored.
RE: Read Enable
RE is a read enable clock input in the FIFO mode. RE enables or disables both internal read address pointers and
data-out buffers. When
RE is low, the internal read address pointer is incremented synchronously with RCLK.
When
RE is high, even if the RCLK is input, the internal read address pointer is not incremented.
The output pins are enabled in the read cycle of the Block Access mode when this pin (
RE) is low “L”.
RR: Read Reset
RR is a read reset control input in the FIFO mode. Read address reset modes are defined when RR level is high
according to the “FUNCTION TABLE for read”.
In the Block Access mode, the RR signal is ignored.
RXINC: Read X Address Increment
RXINC is a read X address (or line address) increment control input in the FIFO mode. In the read address reset
cycle, defined by RR high, the X address (or line address) is incremented by 1 when RXINC is pulled high with
RADE/RX low.
In the Block Access mode, the RXINC signal is ignored.
RADE/RX: Read Address Enable/Read X Address Reset Logic Function
RADE/RX is a dual function control input in the FIFO mode. RADE, one of the two functions of RADE/RX, is a
read address enable input. In the read address set cycle, X address (or line address) input from the RXAD pin is
latched into internal read X address register synchronously with RCLK.
RX, the second function of RADE/RX, works as an element to set read X address (or line address) reset mode. In
an address reset mode cycle, defined by RR high, read X address is set to 0 when RADE/RX is pulled high with
RXINC low.
In the Block Access mode, the RADE/RX signal is ignored.


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