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AN7900T Datasheet(PDF) 4 Page - Panasonic Semiconductor

Part No. AN7900T
Description  3-pin Negative Output Voltage Regulators 1A Type
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Maker  PANASONIC [Panasonic Semiconductor]
Homepage  http://www.panasonic.com/industrial/
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AN7900T Datasheet(HTML) 4 Page - Panasonic Semiconductor

   
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4
VO
–8.3
V
–8
VO
V
REGIN
160
mV
6
mV
REGL
mV
12
mV
mA
2.2
2
Ibias
mA
mA
52
Vno
dB
1
0.5
80
–8.4
160
80
4.5
56
–7.7
–7.6
RR
V
1.1
A
2.1
4
71
– 0.6
typ
Output voltage
Output voltage tolerance
Line regulation
Load regulation
Bias current
Input bias fluctuation
Load bias current fluctuation
Output noise voltage
Ripple rejection ratio
Minimum input/output voltage difference
Peak output current
Output voltage temperature coefficient
Parameter
Symbol
Condition
min
max
Unit
VI
=–10 to –23V,
IO
=5mA to 1A, P
D
*
VI
=–10.5 to –25V, T
j
=25˚C
IO
=5mA to 1.5A, T
j
=25˚C
IO
=250 to 750mA, T
j
=25˚C
VI
=–11 to –17V, T
j
=25˚C
Tj
=25˚C
VI
=–10.5 to –25V, T
j
=25˚C
µV
IO
=5mA to 1A, T
j
=25˚C
f
=10Hz to 100kHz, Ta=25˚C
VI
=–11 to –21V, I
O
=100mA, f=120Hz
IO
=1A, T
j
=25˚C
Tj
=25˚C
IO
=5mA, T
j
=0 to 125˚C
Tj
=25˚C
∆I
bias (IN)
∆I
bias (L)
VDIF (min.)
IO (Peak)
mV/˚C
∆V
O/Ta
Note 1) The specified condition Tj
=25˚C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI
=–14V, I
O
=500mA, C
I
=2µF, C
O
=1µF, T
j
=0 to 125˚C
* AN7900T series : 15W, AN7900F series : 10.25W
s Electrical Characteristics (Ta
=25˚C) (continued)
• AN7908T/AN7908F (–8V Type)
<
=
VO
–9.35
V
–9
VO
V
REGIN
180
mV
7
mV
REGL
mV
12
mV
mA
2.2
2
Ibias
mA
mA
58
dB
1
0.5
90
–9.45
180
90
4.5
56
–8.65
–8.55
RR
V
1.1
A
2.1
4
71
–0.6
typ
Output voltage tolerance
Input bias fluctuation
Load bias current fluctuation
Output noise voltage
Ripple rejection ratio
Minimum input/output voltage difference
Peak output current
Output voltage temperature coefficient
Parameter
Symbol
Condition
min
max
Unit
Output voltage
Line regulation
Load regulation
Bias current
Vno
VI
=–11.5 to –24V,
IO
=5mA to 1A, P
D
*
VI
=–11.5 to –26V, T
j
=25˚C
IO
=5mA to 1.5A, T
j
=25˚C
IO
=250 to 750mA, T
j
=25˚C
VI
=–12 to –18V, T
j
=25˚C
Tj
=25˚C
VI
=–11.5 to –26V, T
j
=25˚C
µV
IO
=5mA to 1A, T
j
=25˚C
f
=10Hz to 100kHz, Ta=25˚C
VI
=–12 to –22V, I
O
=100mA, f=120Hz
IO
=1A, T
j
=25˚C
Tj
=25˚C
IO
=5mA, T
j
=0 to 125˚C
Tj
=25˚C
∆I
bias (IN)
∆I
bias (L)
VDIF (min.)
IO (Peak)
mV/˚C
∆V
O/Ta
Note 1) The specified condition Tj
=25˚C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI
=–15V, I
O
=500mA, C
I
=2µF, C
O
=1µF, T
j
=0 to 125˚C
* AN7900T series : 15W, AN7900F series : 10.25W
• AN7909T/AN7909F (–9V Type)
<
=


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