PEDR27V6466F-01-08

1Semiconductor

MR27V6466F

9/39

ADDRESSING MAP

(1)

WORD = “H”: x32 Organization

Pin Name

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

Row Address

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

RA8

RA9

RA10

RA11

RA12

Column Address

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

X

XXXX

( X = Don’t Care)

(2)

WORD = “L”: x16 Organization

Pin Name

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

Row Address

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

RA8

RA9

RA10

RA11

RA12

Column Address

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

XXXX

( X = Don’t Care)

(3) Programming

Address displayed on

programmer: x16

Ad0

Ad1

Ad2

Ad3

Ad4

Ad5

Ad6

Ad7

Ad8

Ad9

Ad10 Ad11 Ad12

Device Address: x16

STO = “H”, AMPX = “L”

CAP0

CAP1

CAP2

CAP3

CAP4

CAP5

CAP6

CAP7

CAP8

A0

A1

A2

A3

Address (STO = “L”)

WORD = “L”: x16

CA0

Note2

CA1

Note3

CA2

CA3

CA4

CA5

CA6

CA7

CA8

RA0

RA1

RA2

RA3

Address (STO = “L”)

WORD = “H”: x32

Note1 CA0

Note4

CA1

Note5

CA2

CA3

CA4

CA5

CA6

CA7

RA0

RA1

RA2

RA3

Address displayed on

programmer: x16

Ad13 Ad14 Ad15 Ad16 Ad17 Ad18 Ad19 Ad20 Ad21

Device Address: x16

STO = “H”, AMPX = “L”

A4

A5

A6

A7

A8

A9

A10

A11

A12

Address (STO = “L”)

WORD = “L”: x16

RA4

RA5

RA6

RA7

RA8

RA9

RA10

RA11

RA12

Address (STO = “L”)

WORD = “H”: x32

RA4

RA5

RA6

RA7

RA8

RA9

RA10

RA11

RA12

Users of MR27V6466F are recommended to study the relationship between "Address displayed on programmer"

and "Address (STO = "L")" ignoring "Device Address: x16, STO = "H"".

The order of data on Synchronous Read operation (STO="L") is checked on this table.

"Device Address : x16, STO = "H"" will be utilized to design socket adapter on programmer or to check boards

designed to mount blank OTP and program OTP on board.

OKI will supply a socket adapter to program MR27V6466F as conventional x16 standard OTP. The users and the

venders of programmer who use the socket adapter can ignore "Device Address: x16, STO = "H"".

The persons who use 32Mbit SOTP and 64Mbit SOTP must be careful to distinguish the socket adapters for

64Mbit from one for 32Mbit. The difference is caused from the additional assignment of column address and 1 bit

shift of row address on 64Mbit SOTP

Note

1. A0 in programmer distinguishes upper word (x16) or lower word (x16) of Double word (x32).

On word (x16) organization the address of device corresponds to the address of programmer.

On double word (x32) organization the address numeral code of device is half of that in programmer, and

output on DQ0 to DQ15 is lower word (A0 = "0") and output on DQ16 to DQ31 is upper word (A0 = "1").

2. CA1 is MSB of burst read on condition of WORD = "L" and BL = 4.

3. CA2 is MSB of burst read on condition of WORD = "L" and BL = 8.

4. CA1 is MSB of burst read on condition of WORD = "H" and BL = 4.

5. CA2 is MSB of burst read on condition of WORD = "H" and BL = 8.